參數(shù)資料
型號: MAXQ7665BATM+T
廠商: Maxim Integrated Products
文件頁數(shù): 21/47頁
文件大小: 0K
描述: IC MCU-BASED DAS 16BIT 48-TQFN
標準包裝: 2,500
系列: MAXQ®
核心處理器: RISC
芯體尺寸: 16-位
速度: 8MHz
連通性: CAN,LIN,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 256 x 16
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.25 V
數(shù)據(jù)轉換器: A/D 8x12b,D/A 1x12b
振蕩器型: 內部
工作溫度: -40°C ~ 125°C
封裝/外殼: 48-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
MAXQ7665A–MAXQ7665D
16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
28
_______________________________________________________________________________________
DIVIDE
BY 4
D7
D6
D5
D4
D3
D2
D1
D0
0
1
LOAD
CLOCK
TRANSMIT SHIFT REGISTER
S0
LATCH
RECEIVE DATA BUFFER
WR
SBUF0
RD
D7
D6
D5
D4
D3
D2
D1
D0
CLOCK
RECEIVE SHIFT REGISTER
SI
RESET
BAUD
CLOCK
LOAD
SERIAL
BUFFER
LOAD
SERIAL I/O
CONTROL
INTS
SHIFT
READ
SERIAL
BUFFER
TI
FLAG =
SCON0.1
RI
FLAG =
SCON0.0
DIVIDE
BY 16
LDSBUF
RDSBUF
01
SBUF0
SMOD
URX
INPUT
SYSCLK
DIVIDE
BY 16
BIT
DETECTION
UTX
OUTPUT
RB8 =
SCON0.2
BAUD CLOCK
GENERATOR
START
STOP
START
SERIAL
INTERRUPT
DATA BUS
Figure 11b. UART Asynchronous Mode (Mode 1)
detection. Table 1 summarizes the operating characteris-
tics as well as the maximum baud rate of each mode.
JTAG Interface Bus
The joint test action group (JTAG) IEEE 1149.1 stan-
dard defines a unique method for in-circuit testing and
programming. The MAXQ7665A–MAXQ7665D conform
to this standard, implementing an external test access
port (TAP) and internal TAP controller for communica-
tion with a JTAG bus master, such as an automatic test
equipment (ATE) system. For detailed information on
the TAP and TAP controller, refer to
IEEE Standard
1149.1 on the IEEE website at http://standards.ieee.org.
The JTAG on the MAXQ7665A–MAXQ7665D is used for
in-circuit emulation and debug support, but does not
support boundary scan test capability.
The TAP controller communicates synchronously with
the host system (bus master) through four digital I/O
pins: test mode select (TMS), test clock (TCK), test
data input (TDI), and test data output (TDO). The inter-
nal TAP module consists of several shift registers and a
MODE
TYPE
BAUD CLOCK
START BITS
DATA BITS
STOP BITS
MAX BAUD RATE AT
8MHz
Mode 0
Synchronous
4 or 12 clock
N/A
8
N/A
2Mbps
Mode 1
Asynchronous
Baud generation
1
8
1
250kbps
Mode 2
Asynchronous
32 or 64 clock
1
8 + 1
1
250kbps
Mode 3
Asynchronous
Baud generation
1
8 + 1
1
250kbps
Table 1. Operating Characteristics and Mode Baud Rate
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