參數(shù)資料
型號(hào): MAXQ7665BATM+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 18/47頁(yè)
文件大小: 0K
描述: IC MCU-BASED DAS 16BIT 48-TQFN
標(biāo)準(zhǔn)包裝: 2,500
系列: MAXQ®
核心處理器: RISC
芯體尺寸: 16-位
速度: 8MHz
連通性: CAN,LIN,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 8
程序存儲(chǔ)器容量: 64KB(32K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 16
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 48-VFQFN 裸露焊盤(pán)
包裝: 帶卷 (TR)
MAXQ7665A–MAXQ7665D
16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
______________________________________________________________________________________
25
Note: The MAXQ7665A–MAXQ7665D do not have sec-
ondary timer I/O pins (such as T0B and T1B) that are
present in some other MAXQ products.
16-Bit x 16-Bit Hardware Multiplier
A hardware multiplier supports high-speed multiplica-
tions. The multiplier is capable of completing a 16-bit x
16-bit multiply in a single cycle and contains a 48-bit
accumulator that requires one more cycle. The multipli-
er is not part of the MAXQ core function but a peripher-
al that performs seven different multiply operations
without interfering with the normal core functions:
Unsigned 16-bit multiplication (one cycle)
Unsigned 16-bit multiplication and accumulation
(two cycles)
Unsigned 16-bit multiplication and subtraction (two
cycles)
Signed 16-bit multiplication (one cycle)
Signed 16-bit multiplication and negate (one cycle)
Signed 16-bit multiplication and accumulation (two
cycles)
Signed 16-bit multiplication and subtraction (two
cycles)
Figure 9 illustrates the simplified hardware multiplier cir-
cuitry. Two 16-bit parallel-load registers and a 48-bit
accumulator are used: operand A (MA), operand B
(MB), and accumulator (MC). The accumulator is formed
by three 16-bit parallel registers (MC2, MC1, and MC0).
The overflow bit is organized in the MCNT status/control
register. The multiplicand and the multiplier are initially
loaded into the MA and MB registers, respectively.
Loading the required operands triggers the respective
multiply, multiply-accumulate/subtract or multiply-negate
operation. The multiply operation completes in a single
cycle with the results in the read-only MC1R/MC0R reg-
ister. The multiply-accumulate/subtract operation
requires one extra wait cycle for the results to be stable
in the MC2, MC1, and MC0 registers.
The main arithmetic unit is the 16-bit x 16-bit multiplier,
which processes operands feeding from the MA and
MB registers and generates a 32-bit final product. The
product value goes through the 32-bit adder to perform
final accumulation with zeroes for multiply operation or
with the contents from the MC1 and MC0 registers for
multiply-accumulation. The final sum is accessible
directly from the accumulator.
To support negate operations including signed multiply-
negate and signed and unsigned multiply-subtract, the
operand in MA is negated by 1’s complement operation
before being supplied to the arithmetic unit and the par-
tial product terms are sign corrected. Refer to the
MAXQ7665/MAXQ7666 User’s Guide for more detailed
information.
CAN Interface Bus
The MAXQ7665A–MAXQ7665D incorporate a CAN
controller that is fully compliant with the CAN 2.0B
specification.
The C interface to the CAN controller is broken into
two groups of registers. To simplify the software associ-
ated with the operation of the CAN controllers, most of
the global CAN status and controls as well as the indi-
vidual message center control/status registers are
located in the peripheral register map. The remaining
registers associated with the data identification, identifi-
cation masks, format, and data are located in a dual
port memory to allow the CAN controller and the
processor access to the required functions. The CAN
controller can directly access the dual port memory. A
dedicated interface is incorporated to support dual port
memory accessing by the processor through the CAN
0 data pointer (C0DP) and the CAN 0 data buffer
(C0DB) special function registers.
MULTIPLIER
MCNT
SUS
MMAC
MSUB
OPCS
SQU
CLD
MCW
MC0
MC1
MC2
OVERFLOW
MA
15
0
MB
15
0
15 0
15
0
15
0
MC0R
MC1R
15 0
15
0
Figure 9. 16-Bit Hardware Multiplier Functional Diagram
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