參數(shù)資料
型號: MAXQ7665BATM+T
廠商: Maxim Integrated Products
文件頁數(shù): 19/47頁
文件大?。?/td> 0K
描述: IC MCU-BASED DAS 16BIT 48-TQFN
標準包裝: 2,500
系列: MAXQ®
核心處理器: RISC
芯體尺寸: 16-位
速度: 8MHz
連通性: CAN,LIN,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 256 x 16
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.25 V
數(shù)據(jù)轉換器: A/D 8x12b,D/A 1x12b
振蕩器型: 內部
工作溫度: -40°C ~ 125°C
封裝/外殼: 48-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
MAXQ7665A–MAXQ7665D
16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
26
_______________________________________________________________________________________
CAN 0 CONTROLLER BLOCK DIAGRAM
DUAL PORT MEMORY
CAN PROCESSOR
CAN 0 PERIPHERAL REGISTERS
MESSAGE CENTERS 1–15
BUS ACTIVITY WAKE-UP
8-BIT
Rx
CRC
CHECK
BIT
DESTUFF
Rx
SHIFT
BIT
TIMING
CANRXD
CANTXD
MESSAGE CENTER 2
ARBITRATION 0–3
FORMAT
DATA 0–7
MESSAGE CENTER 1
ARBITRATION 0–3
FORMAT
DATA 0–7
MESSAGE CENTER 15
CONTROL/STATUS/MASK REGISTERS
ARBITRATION 0–3
MEDIA ARBITRATION 0–1
EXT GLOBAL MASK 0–3
MEDIA ID MASK 0–1
STD GLOBAL MASK 0–1
BUS TIMING 0–1
MSG15 MASK 0–3
FORMAT
DATA 0–7
MESSAGE CENTER 14
ARBITRATION 0–3
FORMAT
DATA 0–7
CAN 0 TRANSMIT MSG ACK
CAN 0 INTERRUPT REGISTER
CAN 0 STATUS REGISTER
CAN 0 RECEIVE MSG ACK
CAN 0 OPERATION CONTROL
CAN 0 CONTROL REGISTER
CAN 0 DATA POINTER
CAN 0 MESSAGE 1–15
CONTROL REGISTERS
CAN 0 DATA BUFFER
CAN 0 TRANSMIT ERROR
COUNTER
CAN 0 RECEIVE ERROR
COUNTER
CAN INTERRUPT
SOURCES
8-BIT
Tx
CRC
GENERATE
CAN
PROTOCOL
FSM
BIT
STUFF
Tx
SHIFT
MAXQ7665A–MAXQ7665D
Figure 10. CAN 0 Controller Block Diagram
CAN Functional Description
The basic functions covered by the CAN controller
include the use of 11-bit standard or 29-bit extended
acceptance identifiers, as programmed by the C for
each message center, as shown in Figure 10. The CAN
unit provides storage for up to 15 messages, with the
standard 8-byte data field, in each message.
Each of the first 14 message centers is programmable
in either transmit or receive mode. Message center 15
is designed as a receive-only message center with a
buffer FIFO arrangement to help prevent the inadver-
tent loss of data when the C is busy and is not
allowed time to retrieve the incoming message prior to
the acceptance of a second message into message
center 15. Message center 15 also utilizes an indepen-
dent set of mask registers and identification registers,
which are only applied once an incoming message has
not been accepted by any of the first 14 message cen-
ters. A second filter test is also supported for all mes-
sage centers (1–15) to allow the CAN controller to use
two separate 8-bit media masks and media arbitration
fields to verify the contents of the first 2 bytes of data of
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