參數(shù)資料
型號： MAX7456EUI+T
廠商： Maxim Integrated Products
文件頁數(shù)： 44/44頁
文件大?。?/td> 0K
描述： IC DISPLAY 1CH W/EEPROM 28TSSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類型： OSD（屏幕顯示）視頻發(fā)生器
應(yīng)用： 安全系統(tǒng)，視頻路由
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.173"，4.40mm 寬）裸露焊盤
供應(yīng)商設(shè)備封裝： 28-TSSOP 裸露焊盤
包裝： 帶卷 (TR)
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
Pin Description
PIN
NAME
FUNCTION
1, 2, 13–16,
27, 28
N.C.
No Connection. Not internally connected.
3
DVDD
Digital Power-Supply Input. Bypass to DGND with a 0.1F capacitor.
4
DGND
Digital Ground
5
CLKIN
Crystal Connection 1. Connect a parallel resonant, fundamental mode crystal between CLKIN and XFB
for use as a crystal oscillator, or drive CLKIN directly with a 27MHz system reference clock.
6
XFB
Crystal Connection 2. Connect a parallel resonant, fundamental mode crystal between CLKIN and XFB
for use as a crystal oscillator, or leave XFB unconnected when driving CLKIN with a 27MHz system
reference clock.
7
CLKOUT
Clock Output. 27MHz logic-level output system clock.
8
CS
Active-Low Chip-Select Input. SDOUT goes high impedance when CS is high.
9
SDIN
Serial Data Input. Data is clocked in at rising edge of SCLK.
10
SCLK
Serial Clock Input. Clocks data into SDIN and out of SDOUT. Duty cycle must be between 40% and 60%.
11
SDOUT
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high.
12
LOS
Loss-of-Sync Output (Open-Drain). LOS goes high when the VIN sync pulse is lost for 32 consecutive
lines. LOS goes low when 32 consecutive valid sync pulses are received. Connect to a 1k
Ω pullup
resistor to DVDD or another positive supply voltage suitable for the receiving device.
17
VSYNC
Vertical Sync Output (Open-Drain). VSYNC goes low following the video input’s vertical sync interval.
VSYNC is either recovered from VIN or internally generated when in internal sync mode. Connect to a
1k
Ω pullup resistor to DVDD or another positive supply voltage suitable for the receiving device.
18
HSYNC
Horizontal Sync Output (Open-Drain). HSYNC goes low following the video input’s horizontal sync
interval. HSYNC is either recovered from VIN or internally generated when in internal sync mode. Connect
to a 1k
Ω pullup resistor to DVDD or another positive supply voltage suitable for the receiving device.
19
RESET
System Reset Input. The minimum RESET pulse width is 50ms. All SPI registers are reset to their default
values after 100s following the rising edge of RESET. These registers are not accessible for reading or
writing during that time. The display memory is reset to its default value of 00H in all locations after 20s
following the rising edge of RESET.
20
AGND
Analog Ground
21
AVDD
Analog Power-Supply Input. Bypass to AGND with a 0.1F capacitor.
22
VIN
PAL or NTSC CVBS Video Input
23
PGND
Driver Ground. Connect to AGND at a single point.
24
PVDD
Driver Power-Supply Input. Bypass to PGND with a 0.1F capacitor.
25
SAG
Sag Correction Input. Connect to VOUT if not used. See Figure 1b.
26
VOUT
Video Output
—EP
Exposed Pad. Internally connected to AGND. Connect EP to the AGND plane for improved heat
dissipation. Do not use EP as the only ground connection.
MAX7456
Maxim Integrated
9
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