參數(shù)資料
型號(hào): MAX7456EUI+T
廠商: Maxim Integrated Products
文件頁數(shù): 18/44頁
文件大?。?/td> 0K
描述: IC DISPLAY 1CH W/EEPROM 28TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: OSD(屏幕顯示)視頻發(fā)生器
應(yīng)用: 安全系統(tǒng),視頻路由
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.173",4.40mm 寬)裸露焊盤
供應(yīng)商設(shè)備封裝: 28-TSSOP 裸露焊盤
包裝: 帶卷 (TR)
Video Mode 0 Register (VM0)
Write address = 00H, read address = 80H.
Read/write access: unrestricted.
To write to this register, the following conditions must
be met:
1) STAT[5] = 0, the character memory (NVM) is not
busy.
2) DMM[2] = 0, the display memory (SRAM) is not
in the process of being cleared.
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
BIT
DEFAULT
FUNCTION
7
0
Don’t Care
60
Video Standard Select
0 = NTSC
1 = PAL
5, 4
00
Sync Select Mode (Table 1)
0x = Autosync select (external sync when LOS = 0 and internal sync when LOS = 1)
10 = External
11 = Internal
30
Enable Display of OSD Image
0 = Off
1 = On
20
Vertical Synchronization of On-Screen Data
0 = Enable on-screen display immediately
1 = Enable on-screen display at the next VSYNC
10
Software Reset Bit
When this bit is set, all registers are set to their default values and the display memory is cleared.
When a stable 27MHz clock is present, this bit is automatically cleared internally after typically
100s. The user does not need to write a 0 afterwards. SPI operations should not be performed
during this time or unpredictable results may occur. The status of the bit can be checked by
reading this register after typically 100s. This register is not accessible for writing until the display
memory clear operation is finished (typically 20s).
00
Video Buffer Enable
0 = Enable
1 = Disable (VOUT is high impedance)
X = Don’t care.
MAX7456
Maxim Integrated
25
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