參數(shù)資料
型號: MAX7456EUI+T
廠商: Maxim Integrated Products
文件頁數(shù): 16/44頁
文件大?。?/td> 0K
描述: IC DISPLAY 1CH W/EEPROM 28TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: OSD(屏幕顯示)視頻發(fā)生器
應(yīng)用: 安全系統(tǒng),視頻路由
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.173",4.40mm 寬)裸露焊盤
供應(yīng)商設(shè)備封裝: 28-TSSOP 裸露焊盤
包裝: 帶卷 (TR)
Software Reset
The MAX7456 features a Software Reset bit (VM0[1])
that, when set high, clears the display memory and
resets all registers to their default values except the
OSD Black Level register (OSDBL). After 100s (typi-
cal), STAT[6] can be polled to verify that the reset
process is complete.
Hardware Reset
The MAX7456 provides a hardware reset input (RESET)
that functions the same as the POR. All registers are
reset to their default values and are not accessible for
reading/writing when RESET is driven low. The resetting
process requires a
≥ 50ms wide RESET pulse, and no
other activities are allowed during this interval. All SPI
registers are reset to their default values 100s after the
rising edge of RESET. The display memory is reset to
its default value of 00H in all locations 20s after the ris-
ing edge of RESET. RESET takes precedence over the
Software Reset bit. After RESET has been deasserted,
STAT[6] can be polled to verify that the reset sequence
is complete.
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
SUPPLY
VOLTAGE
XTAL
OSCILLATOR
50ms
4.75V
0V
SPI
REGISTER
RESET
100
μs
50ms
DISPLAY
MEMORY
CLEAR
20
μs
POWER
ON
POWER
STABLE
CLOCK
STABLE
POWER-ON
RESET START
POR DEFAULT
STATE
Figure 22. Power-On Reset Sequence
MAX7456
Maxim Integrated
23
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