Note 1: See the standard test circuits of Figure 1. R
參數(shù)資料
型號： MAX7456EUI+T
廠商： Maxim Integrated Products
文件頁數(shù)： 40/44頁
文件大?。?/td> 0K
描述： IC DISPLAY 1CH W/EEPROM 28TSSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類型： OSD（屏幕顯示）視頻發(fā)生器
應(yīng)用： 安全系統(tǒng)，視頻路由
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.173"，4.40mm 寬）裸露焊盤
供應(yīng)商設(shè)備封裝： 28-TSSOP 裸露焊盤
包裝： 帶卷 (TR)
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
Note 1: See the standard test circuits of Figure 1. RL = 75Ω, unless otherwise specified. All digital input signals are timed from a
voltage level of (VIH + VIL) / 2. All parameters are tested at TA = +85°C and values through temperature range are guaran-
teed by design.
Note 2: The input-voltage operating range is the input range over which the output signal parameters are guaranteed (Figure 3).
Note 3: The input-voltage sync detection range is the input composite video range over which an input sync signal is properly
detected and the OSD signal appears at VOUT. However, the output voltage specifications are not guaranteed for input sig-
nals exceeding the maximum specified in the input operating voltage range (Figure 3).
TIMING CHARACTERISTICS (continued)
(VAVDD = +4.75V to +5.25V, VDVDD = +4.75V to +5.25V, VPVDD = +4.75V to +5.25V, TA = TMIN to TMAX. Typical values are at VAVDD
= VDVDD = VPVDD = +5V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NTSC external sync mode, Figure 4
400
VOUT Sync to VSYNC Rising
Edge Delay
tVOUT-VSR
PAL external sync mode, Figure 6
425
ns
NTSC internal sync mode, Figure 5
40
VSYNC Falling Edge to VOUT
Sync Delay
tVSF-VOUT
PAL internal sync mode, Figure 7
45
ns
NTSC internal sync mode, Figure 5
32
VSYNC Rising Edge to VOUT
Sync Delay
tVSR-VOUT
PAL internal sync mode, Figure 7
30
ns
VOUT Sync to HSYNC Falling
Edge Delay
tVOUT-HSF
NTSC and PAL external sync mode,
Figure 8
310
ns
VOUT Sync to HSYNC Rising
Edge Delay
tVOUT-HSR
NTSC and PAL external sync mode,
Figure 8
325
ns
HSYNC Falling Edge to VOUT
Sync Delay
tHSF-VOUT
NTSC and PAL internal sync mode,
Figure 9
115
ns
HSYNC Rising Edge to VOUT
Sync Delay
tHSR-VOUT
NTSC and PAL internal sync mode,
Figure 9
115
ns
All Supplies High to CS Low
tPUD
Power-up delay
50
ms
NVM Write Busy
tNVW
12
ms
CIN
0.1
μF
RIN
75
Ω
a) INPUT TEST CIRCUIT
VIN
SAG
CL
22pF
RL
150
Ω
b) ONE STANDARD VIDEO LOAD, DC-COUPLED
VOUT
SIGNAL
GEN
MAX7456
Figure 1. Standard Test Circuits
MAX7456
Maxim Integrated
5
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