參數(shù)資料
型號: MAX7456EUI+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/44頁
文件大?。?/td> 0K
描述: IC DISPLAY 1CH W/EEPROM 28TSSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
類型: OSD(屏幕顯示)視頻發(fā)生器
應用: 安全系統(tǒng),視頻路由
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.173",4.40mm 寬)裸露焊盤
供應商設備封裝: 28-TSSOP 裸露焊盤
包裝: 帶卷 (TR)
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
Video Timing Generator
The video timing generator is a digital circuit generat-
ing all internal and external (VSYNC and HSYNC) tim-
ing signals. VSYNC and HSYNC can be synchronized
to VIN, or run independently of any input when in inter-
nal sync mode. The video timing generator can gener-
ate NTSC or PAL timing using the same 27MHz crystal
(see Figures 4–9).
Crystal Oscillator
The internal crystal oscillator generates the system
clock used by the video timing generator. The oscillator
uses a 27MHz crystal or can be driven by an external
27MHz TTL clock at CLKIN. For external clock mode,
connect the 27MHz TTL input clock to CLKIN and leave
XFB unconnected.
Display Memory (SRAM)
The display memory stores 480 character addresses
that point to the characters stored in the NVM character
memory. The content of the display memory is user-
programmable through the SPI-compatible serial inter-
face. The display-memory address corresponds to a
fixed location on a monitor (see Figure 10). Momentary
breakup of the OSD image can be prevented by writing
to the display memory during the vertical blanking inter-
val. This can be achieved by using VSYNC as an inter-
rupt to the host processor to initiate writing to the
display memory.
tVOUT-VSF
1/2H
VERTICAL SYNCHRONIZATION
PULSE INTERVAL
VOUT
(ODD FIELD)
VOUT
(EVEN FIELD)
VSYNC
HSYNC
(ODD FIELD)
HSYNC
(EVEN FIELD)
50%
tVOUT-VSR
50%
Figure 4. VOUT, VSYNC, and HSYNC Timing (NTSC, External Sync Mode)
MAX7456
12
Maxim Integrated
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