參數(shù)資料
型號: MAX5858AECM+D
廠商: Maxim Integrated Products
文件頁數(shù): 6/25頁
文件大小: 0K
描述: IC DAC 10BIT DUAL 300MSPS 48TQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 250
設(shè)置時間: 11ns
位數(shù): 10
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 816mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-TQFP 裸露焊盤(7x7)
包裝: 托盤
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 300M
MAX5858A
Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
14
______________________________________________________________________________________
Detailed Description
The MAX5858A dual, high-speed, 10-bit, current-output
DAC provides superior performance in communication
systems requiring low-distortion analog-signal recon-
struction. The MAX5858A combines two DAC cores with
2x/4x programmable digital interpolation filters, a PLL
clock multiplier, divide-by-N clock output, and an on-
chip 1.24V reference. The current outputs of the DACs
can be configured for differential or single-ended opera-
tion. The full-scale output current range is adjustable
from 2mA to 20mA to optimize power dissipation and
gain control.
The MAX5858A accepts an input data rate of up to
165MHz or a DAC conversion rate of up to 300MHz. The
inputs are latched on the rising edge of the clock where-
as the output latches on the following rising edge.
The two-stage digital interpolation filters are program-
mable to 4x, 2x, or no interpolation. When operating in
4x interpolation mode, the interpolator increases the
DAC conversion rate by a factor of four, providing a
four-fold increase in separation between the recon-
structed waveform spectrum and its first image.
The on-chip PLL clock multiplier generates and distrib-
utes all internal, synchronized high-speed clock signals
required by the input data latches, interpolation filters,
and DAC cores. The on-chip PLL includes phase-detec-
tor, VCO, prescalar, and charge-pump circuits. The PLL
can be enabled or disabled through PLLEN.
The analog and digital sections of the MAX5858A have
separate power-supply inputs (AVDD and DVDD). Also,
a separate supply input is provided for the PLL clock
multiplier (PVDD). AVDD, DVDD, and PVDD operate from
a 2.7V to 3.3V single supply.
The MAX5858A features three modes of operation: nor-
mal, standby, and power-down. These modes allow effi-
cient power management. In power-down, the MAX5858A
consumes only 1A of supply current. Wake-up time from
standby mode to normal DAC operation is 0.7s.
Programming the DAC
An 8-bit control word routed through channel A’s data
port programs the gain matching, interpolator configura-
tion, and operational mode of the MAX5858A. The con-
trol word is latched on the falling edge of CW. Table 1
describes the control word format and function.
The gain on channel A can be adjusted to achieve gain
matching between two channels in a user’s system.
The gain on channel A can be adjusted from +0.4dB to
-0.35dB in steps of 0.05dB by using bits G3 to G0 (see
Table 3).
2x DIGITAL
INTERPOLATION
FILTER
2x DIGITAL
INTERPOLATION
FILTER
INPUT
REGISTER
10-BIT
300MHz
DAC
10
DA9–DA0
OUTPA
PLLF
PLLEN
LOCK
OUTNA
2x DIGITAL
INTERPOLATION
FILTER
2x DIGITAL
INTERPOLATION
FILTER
INPUT
REGISTER
10-BIT
300MHz
DAC
10
DB9–DB0
OUTPB
OUTNB
CONTROL REGISTER
1.2V REFERENCE AND CONTROL AMPLIFIER
PLL CLOCK MULTIPLIER
CLK
CLKXN
CLKXP
F2EN
F1EN
AGND
REFR
RSET
DGND
PGND
REFO
REN
CW
IDE
DVDD
PVDD
AVDD
MAX5858A
Block Diagram
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