參數(shù)資料
型號： MAX5858AECM+D
廠商： Maxim Integrated Products
文件頁數(shù)： 22/25頁
文件大小： 0K
描述： IC DAC 10BIT DUAL 300MSPS 48TQFP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 250
設置時間： 11ns
位數(shù)： 10
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
功率耗散（最大）： 816mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP 裸露焊盤
供應商設備封裝： 48-TQFP 裸露焊盤（7x7）
包裝： 托盤
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 300M
MAX5858A
Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL
6
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = PVDD = 3V, AGND = DGND = PGND = 0, fDAC = 165Msps, no interpolation, PLL disabled, external reference,
VREFO = 1.2V, IFS = 20mA, output amplitude = 0dB FS, differential output, TA = TMIN to TMAX, unless otherwise noted. TA > +25°C
guaranteed by production test. TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
No interpolation
34
2x interpolation
75
fDAC = 60Msps
4x interpolation
72
No interpolation
54
61
2x interpolation
146
fDAC = 165Msps
4x interpolation
140
2x interpolation
172
186
Digital Supply Current (Note 4)
IDVDD
fDAC = 200Msps
4x interpolation
165
178
mA
PLL Power-Supply Voltage
PVDD
2.7
3.3
V
fDAC = 60Msps
17
fDAC = 165Msps
46
52
PLL Supply Current (Note 4)
IPVDD
fDAC = 200Msps, 2x interpolation or 4x
interpolation
55
61
mA
Standby Current
ISTANDBY
(Note 5)
4.4
4.8
mA
Power-Down Current
IPD
(Note 5)
1
A
No interpolation
324
2x interpolation
487
fDAC = 60Msps
4x interpolation
498
No interpolation
438
486
2x interpolation
735
fDAC = 165Msps
4x interpolation
721
2x interpolation
816
Total Power Dissipation
(Note 4)
PTOT
fDAC = 200Msps
4x interpolation
795
mW
Note 1: Including the internal reference voltage tolerance.
Note 2: Measured single ended with 50
load and complementary output connected to ground.
Note 3: Guaranteed by design, not production tested.
Note 4: Tested with an output frequency of fOUT = 5MHz.
Note 5: All digital inputs at 0 or DVDD. Clock signal disabled.
TO OUTPUT
PIN
5pF
0.5mA
1.6V
Figure 1. Load Test Circuit for CLK Outputs
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