- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8772 > MAX3624AETJ+ (Maxim Integrated Products)IC CLOCK GENERATOR PREC 32TQFN PDF資料下載
參數(shù)資料
| 型號(hào)： | MAX3624AETJ+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GENERATOR PREC 32TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送，多路復(fù)用器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL |
| 輸出： | LVCMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 648MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-TQFN-EP（5x5） |
| 包裝： | 托盤 |
MAX3624A
Low-Jitter, Precision Clock Generator
with Four Outputs
6
_______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1
VCCO_B
Power Supply for QB0 and QB1 Clock Outputs. Connect to +3.3V.
2, 19, 24
GND
Supply Ground
3
QB0_OE
LVCMOS/LVTTL Input. Enables/disables QB0 clock output. Connect pin high to enable LVPECL clock
output QB0. Connect low to set QB0 to a logic 0. Has internal 50k
input impedance.
4, 5
SELB1,
SELB0
LVCMOS/LVTTL Input. Controls NB divider setting. Has 50k
input impedance. See Table 2 for
more information.
6
QAC_OE
LVCMOS/LVTTL Input. Enables/disables QA_C clock output. Connect pin high to enable QA_C.
Connect low to set QA_C to a high-impedance state. Has internal 75k
pullup to VCC.
7
MR
LVCMOS/LVTTL Input. Master reset input. Pulse high for > 1μs to reset all dividers. Has internal
75k
pulldown to GND. Not required for normal operation.
8
GNDO_A
Ground for QA_C Output. Connect to supply ground.
9
QA_C
LVCMOS Clock Output
10
VDDO_A
Power Supply for QA_C Clock Output. Connect to +3.3V.
11
VCCO_A
Power Supply for QA Clock Output. Connect to +3.3V.
12
QA
Noninverting Clock Output, LVPECL
13
QA
Inverting Clock Output, LVPECL
14
BYPASS
LVCMOS/LVTTL Input (Active Low). Connect low to bypass the internal PLL. Connect high for
normal operation. When in bypass mode the output dividers are set to divide by 1. Has internal
75k
pullup to VCC.
15, 16
FB_SEL1,
FB_SEL0
LVCMOS/LVTTL Input. Controls M divider setting. See Table 3 for more information. Has internal
75k
pulldown to GND.
17
VCCA
Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering,
this pin can connect to VCC through 10.5
as shown in Figure 2 (requires VCC = +3.3V ±5%).
18
VCC
Core Power Supply. Connect to +3.3V.
20
QA_OE
LVCMOS/LVTTL Input. Enables/disables the QA clock output. Connect this pin high to enable the LVPECL
clock output QA. Connect low to set QA to a logic 0. Has internal 75k
pullup to VCC.
21, 22
SELA0,
SELA1
LVCMOS/LVTTL Input. Controls NA divider setting. See Table 2 for more information. Has 50k
input impedance.
23
QB1_OE
LVCMOS/LVTTL Input. Enables/disables QB1 clock output. Connect pin high to enable LVPECL clock
output QB1. Connect low to set QB1 to a logic 0. Has internal 50k
input impedance.
25
X_OUT
Crystal Oscillator Output
26
X_IN
Crystal Oscillator Input
27
REF_IN
LVCMOS Reference Clock Input. Self-biased to allow AC- or DC-coupling.
28
IN_SEL
LVCMOS/LVTTL Input. Connect high or leave open to use a crystal. Connect low to use REF_IN.
Has internal 75k
pullup to VCC.
29
QB1
LVPECL, Inverting Clock Output
30
QB1
LVPECL, Noninverting Clock Output
31
QB0
LVPECL, Inverting Clock Output
32
QB0
LVPECL, Noninverting Clock Output
—
EP
Exposed Pad. Connect to supply ground for proper electrical and thermal performance.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-J2H-MZ-F4 | CONVERTER MOD DC/DC 52V 25W |
| VE-J5H-MX-B1 | CONVERTER MOD DC/DC 52V 75W |
| VI-2TT-MW-F1 | CONVERTER MOD DC/DC 6.5V 100W |
| VE-J5F-MX-B1 | CONVERTER MOD DC/DC 72V 75W |
| VI-J2H-MZ-F3 | CONVERTER MOD DC/DC 52V 25W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3624AETJ+ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Low Jitter Precision w/Four Outputs RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3624AETJ+T | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Low Jitter Precision w/Four Outputs RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3624AEVKIT+ | 制造商:Microsemi Corporation 功能描述:MAX3624A EVALUATION KIT - Boxed Product (Development Kits) 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:KIT EVALUATION MAX MAX3624A 制造商:Microsemi Corporation 功能描述:KIT EVALUATION MAX MAX3624A |
| MAX3624EVKIT+ | 制造商:Microsemi Corporation 功能描述:MAX3624 EVALUATION KIT - Boxed Product (Development Kits) 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:KIT EVALUATION MAX MAX3624 制造商:Microsemi Corporation 功能描述:KIT EVALUATION MAX MAX3624 |
| MAX3624UTJ+ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。