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參數(shù)資料
| 型號： | MAX3624AETJ+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GENERATOR PREC 32TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 60 |
| 類型： | 時鐘發(fā)生器，扇出配送，多路復用器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL |
| 輸出： | LVCMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 648MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-TQFN-EP（5x5） |
| 包裝： | 托盤 |
Layout Considerations
The inputs and outputs are critical paths for the
MAX3624A, and care should be taken to minimize dis-
continuities on these transmission lines. Here are some
suggestions for maximizing the MAX3624A’s perfor-
mance:
An uninterrupted ground plane should be posi-
tioned beneath the clock I/Os.
Ground pin vias should be placed close to the IC
and the input/output interfaces to allow a return
current path to the MAX3624A and the receive
devices.
Supply decoupling capacitors should be placed
close to the MAX3624A supply pins.
Maintain 100
Ω differential (or 50Ω single-ended)
transmission line impedance out of the MAX3624A.
Use good high-frequency layout techniques and a
multilayer board with an uninterrupted ground
plane to minimize EMI and crosstalk.
Refer to the MAX3624A Evaluation Kit for more information.
Exposed-Pad Package
The exposed pad on the 32-pin TQFN package pro-
vides a very low inductance path for return current trav-
eling to the PCB ground plane. The pad is also
electrical ground on the MAX3624A and must be sol-
dered to the circuit board ground for proper electrical
performance.
Chip Information
TRANSISTOR COUNT: 10,780
PROCESS: BiCMOS
MAX3624A
Low-Jitter, Precision Clock Generator
with Four Outputs
______________________________________________________________________________________
11
10
Ω
10
Ω
ESD
STRUCTURES
QA_C
IN
DISABLE
VDDO_A
Figure 9. Simplified LVCMOS Output Circuit Schematic
MAX3624A
THIN QFN
(5mm
× 5mm)
TOP VIEW
5
6
4
3
20
19
21
V
DDO_A
QA
BYPASS
FB_SEL1
22
QA_C
QB0
QB1
IN_SEL
QB0
REF_IN
X_IN
910
SELB1
12
13
14
15
31
32
30
28
27
26
SELB0
QAC_OE
SELA1
SELA0
QA_OE
GND
V
CCO_A
QB1
11
29
7
18
MR
VCC
8
17
GNDO_A
VCCA
QB0_OE
2
QB1_OE
GND
1
24
GND
FB_SEL0
X_OUT
16
25
VCCO_B
+
*EP
*EXPOSED PAD CONNECTED TO GROUND.
Pin Configuration
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3624AETJ+ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Low Jitter Precision w/Four Outputs RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3624AETJ+T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Low Jitter Precision w/Four Outputs RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3624AEVKIT+ | 制造商:Microsemi Corporation 功能描述:MAX3624A EVALUATION KIT - Boxed Product (Development Kits) 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:KIT EVALUATION MAX MAX3624A 制造商:Microsemi Corporation 功能描述:KIT EVALUATION MAX MAX3624A |
| MAX3624EVKIT+ | 制造商:Microsemi Corporation 功能描述:MAX3624 EVALUATION KIT - Boxed Product (Development Kits) 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:KIT EVALUATION MAX MAX3624 制造商:Microsemi Corporation 功能描述:KIT EVALUATION MAX MAX3624 |
| MAX3624UTJ+ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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