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參數(shù)資料
| 型號： | MAX3624AETJ+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GENERATOR PREC 32TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送，多路復(fù)用器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL |
| 輸出： | LVCMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 648MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-TQFN-EP（5x5） |
| 包裝： | 托盤 |
MAX3624A
Detailed Description
The MAX3624A is a low-jitter clock generator designed
to operate at Ethernet, Fibre Channel, and SONET/SDH
frequencies. It consists of an on-chip crystal oscillator,
PLL, programmable dividers, LVCMOS output buffer,
and LVPECL output buffers. Using a low-frequency
clock (crystal or CMOS input) as a reference, the inter-
nal PLL generates a high-frequency output clock with
excellent jitter performance.
Crystal Oscillator
An integrated oscillator provides the low-frequency ref-
erence clock for the PLL. This oscillator requires an
external crystal connected between X_IN and X_OUT.
Crystal frequency is 19.375MHz to 27MHz.
REF_IN Buffer
An LVCMOS-compatible clock source can be connect-
ed to REF_IN to serve as the reference clock.
The LVCMOS REF_IN buffer is internally biased to allow
AC- or DC-coupling. It is designed to operate up to
320MHz.
PLL
The PLL takes the signal from the crystal oscillator or
reference clock input and synthesizes a low-jitter, high-
frequency clock. The PLL contains a phase-frequency
detector (PFD), a lowpass filter, and a voltage-con-
trolled oscillator (VCO) with a 620MHz to 648MHz oper-
ating range. The VCO output is connected to the PFD
input through a feedback divider. See Table 3 for
divider values. The PFD compares the reference fre-
quency to the divided-down VCO output (fVCO/M) and
generates a control signal that keeps the VCO locked
to the reference clock. The high-frequency VCO output
clock is sent to the output dividers. To minimize noise-
induced jitter, the VCO supply (VCCA) is isolated from
the core logic and output buffer supplies.
Output Dividers
The output divider is programmable to allow a range of
output frequencies. See Table 2 for the divider input
settings. The output dividers are automatically set to
divide by 1 when the MAX3624A is in bypass mode
(BYPASS = 0).
LVPECL Drivers
The high-frequency outputs—QA, QB0, and QB1—are
differential PECL buffers designed to drive transmission
lines terminated with 50
Ω to VCC - 2.0V. The maximum
operating frequency is specified up to 320MHz. Each
output can be individually disabled, if not used. The
outputs go to a logic 0 when disabled.
LVCMOS Driver
QA_C, the LVCMOS output, is designed to drive a sin-
gle-ended high-impedance load. The maximum operat-
ing frequency is specified up to 160MHz. This output
can be disabled by the QAC_OE pin if not used and
goes to a high impedance when disabled.
Reset Logic/POR
During power-on, the power-on reset (POR) signal is
generated to synchronize all dividers. An external mas-
ter reset (MR) signal is not required.
Applications Information
Power-Supply Filtering
The MAX3624A is a mixed analog/digital IC. The PLL
contains analog circuitry susceptible to random noise.
In addition to excellent on-chip power-supply noise
rejection, the MAX3624A provides a separate power-
supply pin, VCCA, for the VCO circuitry. Figure 2 illus-
trates the recommended power-supply filter network for
VCCA. The purpose of this design technique is to
ensure clean input power supply to the VCO circuitry
and to improve the overall immunity to power-supply
noise. This network requires that the power supply is
+3.3V ±5%. Decoupling capacitors should be used on
all other supply pins for best performance.
VCC
VCCA
10.5
Ω
+3.3V
±5%
0.1
μF
10
μF
0.1
μF
Figure 2. Analog Supply Filtering
Low-Jitter, Precision Clock Generator
with Four Outputs
_______________________________________________________________________________________
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3624AETJ+ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Low Jitter Precision w/Four Outputs RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3624AETJ+T | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Low Jitter Precision w/Four Outputs RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3624AEVKIT+ | 制造商:Microsemi Corporation 功能描述:MAX3624A EVALUATION KIT - Boxed Product (Development Kits) 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:KIT EVALUATION MAX MAX3624A 制造商:Microsemi Corporation 功能描述:KIT EVALUATION MAX MAX3624A |
| MAX3624EVKIT+ | 制造商:Microsemi Corporation 功能描述:MAX3624 EVALUATION KIT - Boxed Product (Development Kits) 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:KIT EVALUATION MAX MAX3624 制造商:Microsemi Corporation 功能描述:KIT EVALUATION MAX MAX3624 |
| MAX3624UTJ+ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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