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參數(shù)資料
| 型號(hào)： | MAX3109ETJ+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 50/66頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART |
| 產(chǎn)品培訓(xùn)模塊： | Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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Dual Serial UART with 128-Word FIFOs
MAX3109
54
Maxim Integrated
Transmitter Synchronization Register (TxSynch)
The TxSynch register is used to configure transmitter synchronization with a global SPI or I2C command. One of 16
trigger commands (Table 5) can be selected to be the synchronization trigger source individually for each UART. This
allows simultaneous start of transmission of multiple UARTs that are associated with the same global trigger command.
The synchronized UARTs can be on either a single MAX3109 or multiple devices if they are controlled by a common
SPI interface.
The UARTs start transmission when a global trigger command is received. Start of transmission is considered to be
the falling edge of the START bit at the TX_ output. A delay can optionally be programmed through the SynchDelay1
and SynchDelay2 registers.
TX synchronization is managed through software by transmitting the broadcast trigger Tx command (Table 5) to the
MAX3109 through the SPI or I2C interface. To selectively synchronize ports that are on the same MAX3109 (intrachip
synchronization) or on different MAX3109 (interchip synchronization) devices, up to 16 trigger Tx commands have
been defined (see the Global Command Register (GloblComnd) section for more information).
Bit 7: CLKtoGPIO
The CLKtoGPIO bit is used to provide a buffered replica of the UARTs system clock (i.e., the fractional baud-rate gen-
erator input) to a GPIO. UART0’s clock is routed to GPIO0 and UART1’s clock is routed to GPIO4.
Bit 6: TxAutoDis
Set the TxAutoDis bit high to enable automatic transmitter disabling. When TxAutoDis is set high, the transmitter is
automatically disabled when all data in the TxFIFO has been transmitted. After the transmitter is disabled, the TxFIFO
can then be filled with data that will be transmitted when its assigned trigger command is received, as defined by the
TrigSelx bits.
Bit 5: TrigDelay
Set the TrigDelay bit high to enable delayed start of transmission when a trigger command is received. The UART
starts transmitting data following a delay programmed in SynchDelay1 and SynchDelay2 after receiving the assigned
trigger command.
Bit 4: SynchEn
Set the SynchEn bit high to enable software TX synchronization mode. If SynchEn is set high, the UART starts transmit-
ting data when the assigned trigger command is received and the TxFIFO contains data. Setting SynchEn high forces
the MODE1[1]: TxDisabl bit high and thereby disables the UART’s transmitter. This prevents the transmitter from send-
ing data as soon as the TxFIFO is loaded. Once the TxFIFO has been loaded, the UART starts transmitting data only
upon receiving the assigned trigger command.
Set the SynchEn bit low to disable transmitter synchronization for that UART. If SynchEn is set low, that UART’s trans-
mitter does not start transmission through any trigger command.
Bits 3–0: TrigSelx
The TrigSelx bits assign the trigger command for that UART’s transmitter synchronization when SynchEn is set high.
For example, set TxSynch[3:0] to 0x08 for the UART to be triggered by TX command 8 (0xE8, Table 5).
ADDRESS:
0x20
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
CLKtoGPIO
TxAutoDis
TrigDelay
SynchEn
TrigSel3
TrigSel2
TrigSel1
TrigSel0
RESET
0
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