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參數(shù)資料
| 型號： | MAX3109ETJ+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 35/66頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART |
| 產(chǎn)品培訓模塊： | Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 系列： | * |
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Dual Serial UART with 128-Word FIFOs
MAX3109
40
Maxim Integrated
Line Control Register (LCR)
Bit 7: RTSbit
The RTSbit bit provides direct control of the RTS_ output logic state. If RTSbit is logic 1, then RTS_ is logic 1; if it is
logic 0, then RTS_ is logic 0. RTSbit only works when CLKSource[7]: CLKtoRTS is set low.
Bit 6: TxBreak
Set the TxBreak bit high to generate a line break whereby the TX_ output is held low. TX_ remains low until TxBreak is
set low.
Bit 5: ForceParity
The ForceParity bit enables forced parity that overrides normal parity generation. Set both the LCR[3]: ParityEn and
ForceParity bits high to use forced parity. In forced-parity mode, the parity bit is forced high by the transmitter if the
LCR[4]: EvenParity bit is low. The parity bit is forced low if EvenParity is high. Forced parity mode enables the transmit-
ter to control the address/data bit in 9-bit multidrop communication.
Bit 4: EvenParity
Set the EvenParity bit high to enable even parity for both the transmitter and receiver. If EvenParity is set low, odd
parity is used.
Bit 3: ParityEn
Set the ParityEn bit high to enable the use of a parity bit on the TX_ and RX_ interfaces. Set the ParityEn bit low to dis-
able parity usage.
If ParityEn is set low, then no parity bit is generated by the transmitter or expected by the receiver. If ParityEn is set
high, the transmitter generates the parity bit whose polarity is defined in LCR[4]: EvenParity, and the receiver checks
the parity bit according to the same polarity.
Bit 2: StopBits
The StopBits bit defines the number of stop bits and depends on the length of the word programmed in LCR[1:0]
(Table 1). For example, when StopBits is set high and the word length is 5, the transmitter generates a word with a
stop bit length equal to 1.5 baud periods. Under these conditions, the receiver recognizes a stop bit length greater
than a one-bit duration.
Bits 1 and 0: Lengthx
The Lengthx bits configure the length of the words that the transmitter generates and the receiver checks for at the
asynchronous TX_ and RX_ interfaces (Table 2).
Table 1. StopBits Truth Table
Table 2. Lengthx Truth Table
ADDRESS:
0x0B
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
RTSbit
TxBreak
ForceParity
EvenParity
ParityEn
StopBits
Length1
Length0
RESET
0
1
0
1
StopBits
WORD LENGTH
STOP BIT LENGTH
0
5, 6, 7, 8
1
5
1–1.5
1
6, 7, 8
2
Length1
Length0
WORD LENGTH
0
5
0
1
6
1
0
7
1
8
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