參數(shù)資料
型號： MAX3109ETJ+T
廠商： Maxim Integrated Products
文件頁數(shù)： 38/66頁
文件大?。?/td> 0K
描述： IC UART
產(chǎn)品培訓(xùn)模塊： Obsolescence Mitigation Program
標準包裝： 2,500
系列： *
Dual Serial UART with 128-Word FIFOs
MAX3109
43
Maxim Integrated
FIFO Interrupt Trigger Level Register (FIFOTrgLvl)
Bits 7–4: RxTrigx
The RxTrigx bits allow definition of the receive FIFO threshold level at which the UART generates an interrupt in ISR[3].
This interrupt can be used to signal that either the receive FIFO is nearing overflow or a predefined number of FIFO
locations are available for being read out in one block, depending on the state of the MODE2[2]: RxTrigInv bit.
The selectable threshold resolution is eight FIFO locations, so the actual FIFO trigger level is calculated as 8 x RxTrigx.
The resulting possible trigger-level range is 0 to 120 (decimal).
Bits 3–0: TxTrigx
The TxTrigx bits allow definition of the transmit FIFO threshold level at which the MAX3109 generates an interrupt in
ISR[4]. This interrupt can be used to manage data flow to the transmit FIFO. For example, if the trigger level is defined
near the bottom of the TxFIFO, the host knows that a predefined number of FIFO locations are available for being writ-
ten to in one block. Alternatively, if the trigger level is set near the top of the FIFO, the host is warned when the transmit
FIFO is nearing overflow.
The selectable threshold resolution is eight FIFO locations, so the actual FIFO trigger level is calculated as 8 x TxTrigx.
The resulting possible trigger-level range is 0 to 120 (decimal).
Transmit FIFO Level Register (TxFIFOLvl)
Bits 7–0: TxFLx
The TxFIFOLvl register represents the current number of words in the transmit FIFO.
Receive FIFO Level Register (RxFIFOLvl)
Bits 7–0: RxFLx
The RxFIFOLvl register represents the current number of words in the receive FIFO.
ADDRESS:
0x10
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
RxTrig3
RxTrig2
RxTrig1
RxTrig0
TxTrig3
TxTrig2
TxTrig1
TxTrig0
RESET
1
ADDRESS:
0x11
MODE:
R
BIT
7
6
5
4
3
2
1
0
NAME
TxFL7
TxFL6
TxFL5
TxFL4
TxFL3
TxFL2
TxFL1
TxFL0
RESET
0
ADDRESS:
0x12
MODE:
R
BIT
7
6
5
4
3
2
1
0
NAME
RxFL7
RxFL6
RxFL5
RxFL4
RxFL3
RxFL2
RxFL1
RxFL0
RESET
0
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