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參數(shù)資料
| 型號(hào)： | MAX3109ETJ+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 36/66頁 |
| 文件大小： | 0K |
| 描述： | IC UART |
| 產(chǎn)品培訓(xùn)模塊： | Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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Dual Serial UART with 128-Word FIFOs
MAX3109
41
Maxim Integrated
Receiver Timeout Register (RxTimeOut)
Bits 7–0: TimOutx
The RxTimeOut register allows programming a time delay from after the last (newest) character in the receive FIFO
was received until a receive data timeout interrupt is generated in LSR[0]. The units of TimOutx are measured in com-
plete character frames, which are dependent on the character length, parity, and STOP bit settings, and baud rate. If
the value in RxTimeOut equals zero, a timeout interrupt is not generated.
HDplxDelay Register
The HDplxDelay register allows programming setup and hold times between RTS_ transitions and TX_ output activity in
auto transceiver direction control mode, enabled by setting the MODE1[4]: TrnscvCtrl bit high. The hold time can also
be used to ensure echo suppression in half-duplex communication. HDplxDelay functions in 2x and 4x rate modes.
Bits 7–4: Setupx
The Setupx bits define a setup time for RTS_ to transition high before the transmitter starts transmission of its first char-
acter in auto transceiver direction control mode, enabled by setting the MODE1[4]: TrnscvCtrl bit high. This allows the
MAX3109 to account for skew times between the external transmitter’s enable delay and propagation delays. Setupx
can also be used to fix a stable state on the transmission line prior to the start of transmission.
The resolution of the HDplxDelay setup time delay is one bit interval, or one over the baud rate; this delay is baud-rate
dependent. The maximum delay is 15 bit intervals.
Bits 3–0: Holdx
The Holdx bits define a hold time for RTS_ to be held high after the transmitter ends transmission of its last character
in auto transceiver direction control mode, enabled by setting the MODE1[4]: TrnscvCtrl bit high. RTS_ transitions low
after the hold time delay, which starts after the last STOP bit was sent. This keeps the external transmitter enabled
during the hold time duration.
The Holdx bits also define a delay in echo suppression mode, enabled by setting the MODE2[7]: EchoSuprs bit high.
See the Echo Suppression section for more information.
The resolution of the HDplxDelay hold time delay is one bit interval, or one over the baud rate. Thus, this delay is baud-
rate dependent. The maximum delay is 15 bit intervals.
ADDRESS:
0x0C
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
TimOut7
TimOut6
TimOut5
TimOut4
TimOut3
TimOut2
TimOut1
TimOut0
RESET
0
ADDRESS:
0x0D
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
Setup3
Setup2
Setup1
Setup0
Hold3
Hold2
Hold1
Hold0
RESET
0
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