參數(shù)資料
型號(hào)： MAX3109ETJ+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 13/66頁(yè)
文件大?。?/td> 0K
描述： IC UART
產(chǎn)品培訓(xùn)模塊： Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
系列： *
Dual Serial UART with 128-Word FIFOs
MAX3109
20
Maxim Integrated
The following is an example of how to calculate the divi-
sor. It is based on a required baud rate of 190kbaud
and a reference input frequency of 28.23MHz and 1x
(default) rate mode.
The ideal divisor is calculated as:
D = 28,230,000/(16 x 190,000) = 9.286
hence DIV = 9.
FRACT = ROUND(16 x 0.286) = 5
so DIVMSB = 0x00, DIVLSB = 0x09, and BRGConfig[3:0]
= 0x05.
The resulting actual baud rate can be calculated as:
×
=
×
REF
ACTUAL
f
RateMode
BR
16 D
For this example:
DACTUAL = 9 + 5/16 = 9.3125, RateMode = 1, and
BRACTUAL = 28,230,000/(16 x 9.3125) = 189463 baud.
Thus, the actual baud rate is within 0.28% of the ideal
rate.
2x and 4x Rate Modes
To support higher baud rates than possible with stan-
dard operation using 16x sampling, the MAX3109 offers
2x and 4x rate modes. In these modes, the reference
clock rate only needs to be either 8x or 4x higher than the
baud rate, respectively. In 4x rate mode, each received
bit is only sampled once at the midbit instant instead of
the usual three samples to determine the logic value of
the received bit. This reduces the ability to detect line
noise on the received data in 4x rate mode. The 2x and
4x rate modes are selectable through BRGConfig[5:4].
Note that IrDA encoding and decoding does not operate
in 2x and 4x rate modes.
When 2x rate mode is selected, the actual baud rate is
twice the rate programmed into the baud-rate genera-
tor. If 4x rate mode is enabled, the actual baud rate on
the line is quadruple that of the programmed baud rate
(Figure 8).
Low-Frequency Timer
Each UART has a general-purpose timer that can be
used to generate a low-frequency clock at a GPIO
output and can, for example, be used to drive external
LEDs. The low-frequency clock is a divided replica of the
given UART baud-rate clock. The timer for each UART
is internally routed to the respective GPIO_ output when
enabled by the TIMER2 register as follows:
U
UART0: GPIO1
U
UART1: GPIO5
The clock pulses at the GPIOs are generated at a rate
defined by the baud-rate generator and the timer divider
(Figure 9). The baud-rate generator clock frequency is
divided by (1024 x Timer[14:0]) to produce the GPIO_
clock, where Timer[14:0] is the 15-bit value programmed
into the TIMER1 and TIMER2 registers. The timer output
is 50% duty cycle clock.
Figure 8. 2x and 4x Baud Rates
Figure 9. GPIO_ Clock Pulse Generator
FRACTIONAL
RATE
GENERATOR
fREF
BAUD RATE
BRGConfig[5:4]
DIVLSB
DIVMSB
NOTE: IrDA DOES NOT WORK IN 2x AND 4x MODES.
FRACT
1x, 2x, 4x RATE
MODES
FRACTIONAL
RATE
GENERATOR
fREF
÷TIMERx
GPIO_
TmrToGPIO
÷1024
DIVLSB
DIVMSB
FRACT
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