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參數(shù)資料
| 型號(hào)： | MAX192BEWP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 8/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT SERIAL 20-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS），ADC |
| 分辨率（位）： | 10 b |
| 采樣率（每秒）： | 133k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 單電源 |
| 電源電壓： | ±5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
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MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
16
______________________________________________________________________________________
Reference
Reference-
VREF
Power-
Power-Up
Maximum
Buffer
Capacitor
Down
Delay
Sampling
Compensation
(F)
Mode
(sec)
Rate (ksps)
Mode
Enabled
Internal
Fast
5
26
Enabled
Internal
Full
300
26
Enabled
External
4.7
Fast
See Figure 14c
133
Enabled
External
4.7
Full
See Figure 14c
133
Disabled
Fast
2
133
Disabled
Full
2
133
Table 5. Worst-Case Power-Up Delay Times
PD1
PD0
Device Mode
1
External Clock Mode
1
0
Internal Clock Mode
0
1
Fast Power-Down Mode
0
Full Power-Down Mode
S
SH
HD
DN
N
Device
Reference-Buffer
State
Mode
Compensation
1
Enabled
Internal Compensation
Floating
Enabled
External Compensation
0
Full Power-Down
N/A
tors that will not discharge more than 1/2LSB while shut
down. In shutdown, the capacitor has to supply the cur-
rent into the reference (1.5A typ) and the transient cur-
rents at power-up.
Figures 12a and 12b illustrate the various power-down
sequences in both external and internal clock modes.
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 6, PD1 and
PD0 also specify the clock mode. When software shut-
down is asserted, the ADC will continue to operate in
the last specified clock mode until the conversion is
complete. Then the ADC powers down into a low quies-
cent-current state. In internal clock mode, the interface
remains active and conversion results may be clocked
out while the MAX192 has already entered a software
power-down.
The first logical 1 on DIN will be interpreted as a start
bit, and powers up the MAX192. Following the start bit,
the data input word or control byte also determines
clock and power-down modes. For example, if the DIN
word contains PD1 = 1, then the chip will remain pow-
ered up. If PD1 = 0, a power-down will resume after
one conversion.
Hardware Power-Down
The SHDN pin places the converter into the full
power-down mode. Unlike with the software shutdown
modes, conversion is not completed. It stops coinci-
dentally with SHDN being brought low. There is no
power-up delay if an external reference is used and is
not shut down. The SHDN pin also selects internal or
external reference compensation (see Table 7).
Power-Down Sequencing
The MAX192 auto power-down modes can save con-
siderable power when operating at less than maximum
sample rates. The following discussion illustrates the
various power-down sequences.
Lowest Power at up to 500
Conversions/Channel/Second
The following examples illustrate two different
power-down sequences. Other combinations of clock
rates, compensation modes, and power-down modes
may give lowest power consumption in other applica-
tions.
Figure 14a depicts the MAX192 power consumption for
one or eight channel conversions utilizing full
power-down mode and internal reference compensa-
tion. A 0.01F bypass capacitor at REFADJ forms an
Table 7. Hard-Wired Shutdown and
Compensation Mode
Table 6. Software Shutdown and Clock
Mode
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