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參數(shù)資料
| 型號： | MAX192BEWP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT SERIAL 20-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS），ADC |
| 分辨率（位）： | 10 b |
| 采樣率（每秒）： | 133k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 單電源 |
| 電源電壓： | ±5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
Note 1: Tested at VDD = 5.0V; single-ended, unipolar.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Grounded on-channel; sine wave applied to all off channels.
Note 4: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7: Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: Measured at VSUPPLY + 5% and VSUPPLY - 5% only.
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%, fCLK = 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7F capacitor at VREF pin,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
ISINK = 16mA
ISINK = 5mA
SHDN = open
SHDN = 0V
SHDN = VDD
(Note 5)
VIN = 0V or VDD
CONDITIONS
V
0.3
VOL
Output Voltage Low
0.4
nA
-100
100
SHDN Max Allowed Leakage,
Mid Input
V
2.75
VFLT
SHDN Voltage, Floating
V
1.5
VDD - 1.5
VIM
SHDN Input Mid Voltage
A
-4.0
IINL
SHDN Input Current, Low
A
4.0
IINH
SHDN Input Current, High
V
0.5
VINL
SHDN Input Low Voltage
V
VDD - 0.5
VINH
SHDN Input High Voltage
pF
15
CIN
DIN, SCLK, CS Input Capacitance
A
±1
IIN
DIN, SCLK, CS Input Leakage
V
0.15
VHYST
DIN, SCLK, CS Input Hysteresis
V
0.8
VINL
DIN,SCLK, CS Input Low Voltage
V
2.4
VINH
DIN,SCLK, CS Input High Voltage
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Output Voltage High
VOH
ISOURCE = 1mA
4
V
Three-State Leakage Current
IL
CS = 5V
±10
A
Three-State Leakage Capacitance
COUT
CS = 5V (Note 5)
15
pF
Positive Supply Voltage
VDD
5 ±5%
V
Operating mode
1.5
2.5
mA
Fast power-down
30
70
Positive Supply Current
IDD
Full power-down
2
10
A
Positive Supply Rejection
(Note 9)
PSR
VDD = 5V ±5%; external reference, 4.096V;
full-scale input
±0.06
±0.5
mV
EXTERNAL REFERENCE AT REFADJ
DIGITAL INPUTS (DIN, SCLK,
–
C
—
S
–
,
–
S
—
H
—
D
—
N
–
)
DIGITAL OUTPUTS (DOUT, SSTRB)
POWER REQUIREMENTS
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