參數(shù)資料
型號(hào)： MAX192BEWP+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 13/24頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT SERIAL 20-SOIC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 數(shù)據(jù)采集系統(tǒng)（DAS），ADC
分辨率（位）： 10 b
采樣率（每秒）： 133k
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
電壓電源： 單電源
電源電壓： ±5V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC W
包裝： 帶卷 (TR)
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
20
______________________________________________________________________________________
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
MAX192
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
SHDN
V
DD
SCLK
CS
DIN
SSTRB
DOUT
DGND
AGND
REFADJ
VREF
VDDI, VDDE, VDDSYN, VSTBY
SCK
PCS0
MOSI
MISO
* CLOCK CONNECTIONS NOT SHOWN
VSSI
VSSE
MC68HC16
0.1
F
4.7
F
0.01
F
0.1
F
4.7
F
ANALOG
INPUTS
+5V
+
Figure 19. MAX192 QSPI Connection
TMS320 to MAX192 Interface
Figure 22 shows an application circuit to interface the
MAX192 to the TMS320 in external clock mode. The
timing diagram for this interface circuit is shown in
Figure 23.
Use the following steps to initiate a conversion in the
MAX192 and to read the results:
1)
The TMS320 should be configured with CLKX
(transmit clock) as an active-high output clock and
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR of the TMS320 are
tied together with the SCLK input of the MAX192.
2)
The MAX192 CS is driven low by the XF_ I/O port
of the TMS320 to enable data to be clocked into
DIN of the MAX192.
3)
An 8-bit word (1XXXXX11) should be written to the
MAX192 to initiate a conversion and place the
device into external clock mode. Refer to Table 3
to select the proper XXXXX bit values for your spe-
cific application.
4)
The SSTRB output of the MAX192 is monitored via
the FSR input of the TMS320. A falling edge on the
SSTRB output indicates that the conversion is in
progress and data is ready to be received from
the MAX192.
5)
The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep-
resent the 10-bit conversion result and two sub-
LSBs, followed by four trailing bits, which should
be ignored.
6)
Pull CS high to disable the MAX192 until the next
conversion is initiated.
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