參數(shù)資料
型號(hào)： MAX192BEWP+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 7/24頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT SERIAL 20-SOIC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 數(shù)據(jù)采集系統(tǒng)（DAS），ADC
分辨率（位）： 10 b
采樣率（每秒）： 133k
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
電壓電源： 單電源
電源電壓： ±5V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC W
包裝： 帶卷 (TR)
Power-Down
Choosing Power-Down Mode
You can save power by placing the converter in a
low-current shutdown state between conversions.
Select full power-down or fast power-down mode via
bits 1 and 0 of the DIN control byte with SHDN either
high or floating (see Tables 3 and 6). Pull SHDN low at
any time to shut down the converter completely. SHDN
overrides bits 1 and 0 of DIN word (see Table 7).
Full power-down mode turns off all chip functions that
draw quiescent current, typically reducing IDD to 2A.
Fast power-down mode turns off all circuitry except the
bandgap reference. With the fast power-down mode, the
supply current is 30A. Power-up time can be shortened
to 5s in internal compensation mode.
In both software shutdown modes, the serial interface
remains operational, however, the ADC will not convert.
Table 5 illustrates how the choice of reference-buffer
compensation and power-down mode affects both
power-up delay and maximum sample rate.
In external compensation mode, the power-up time is
20ms with a 4.7F compensation capacitor when the
capacitor is fully discharged. In fast power-down, you
can eliminate start-up time by using low-leakage capaci-
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
______________________________________________________________________________________
15
POWERED UP
FULL
POWER-
DOWN
POWERED
UP
POWERED UP
DATA VALID
(10 + 2 DATA BITS)
DATA VALID
(10 + 2 DATA BITS)
DATA INVALID
VALID
EXTERNAL
INTERNAL
S X X X X X 1 1
S
0 1
X
X X X X X
S
1 1
FAST
POWER-DOWN
MODE
DOUT
DIN
CLOCK
MODE
SHDN
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
SETS FAST
POWER-DOWN
MODE
Figure 12a. Timing Diagram Power-Down Modes, External Clock
FULL
POWER-DOWN
POWERED
UP
POWERED UP
DATA VALID
INTERNAL CLOCK MODE
S X X X X X 1 0
S
0 0
X
S
MODE
DOUT
DIN
CLOCK
MODE
SETS INTERNAL
CLOCK MODE
SETS FULL
POWER-DOWN
CONVERSION
SSTRB
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
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