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參數(shù)資料
| 型號： | MAX192 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Low-Power, 8-Channel,Serial 10-Bit ADC(8通道,133ksps串行10位A/D轉換器) |
| 中文描述： | 低功耗、8通道、串行10位ADC |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 211K |
| 代理商： | MAX192 |
M
Low-Power, 8-Channel,
S erial 10-Bit ADC
16
______________________________________________________________________________________
Reference
Buffer
Reference-
Buffer
Compensation
Mode
VREF
Capacitor
(μF)
Power-
Down
Mode
Power-Up
Delay
(sec)
Maximum
Sampling
Rate (ksps)
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Internal
Internal
External
External
Fast
Full
Fast
Full
Fast
Full
5μ
300μ
See Figure 14c
See Figure 14c
2μ
2μ
26
26
133
133
133
133
4.7
4.7
Table 5. Worst-Case Power-Up Delay Times
PD1
1
1
0
0
PD0
1
0
1
0
Device Mode
External Clock Mode
Internal Clock Mode
Fast Power-Down Mode
Full Power-Down Mode
SHDN
State
1
Floating
0
Device
Mode
Enabled
Enabled
Full Power-Down
Reference-Buffer
Compensation
Internal Compensation
External Compensation
N/A
In external compensation mode, the power-up time is
20ms with a 4.7μF compensation capacitor when the
capacitor is fully discharged. In fast power-down, you
can eliminate start-up time by using low-leakage capaci-
tors that will not discharge more than 1/2LSB while shut
down. In shutdown, the capacitor has to supply the cur-
rent into the reference (1.5μA typ) and the transient cur-
rents at power-up.
Figures 12a and 12b illustrate the various power-down
sequences in both external and internal clock modes.
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 6, PD1 and
PD0 also specify the clock mode. When software shut-
down is asserted, the ADC will continue to operate in
the last specified clock mode until the conversion is
complete. Then the ADC powers down into a low qui-
escent-current state. In internal clock mode, the inter-
face remains active and conversion results may be
clocked out while the MAX192 has already entered a
software power-down.
The first logical 1 on DIN will be interpreted as a start
bit, and powers up the MAX192. Following the start bit,
the data input word or control byte also determines
clock and power-down modes. For example, if the DIN
word contains PD1 = 1, then the chip will remain pow-
ered up. If PD1 = 0, a power-down will resume after
one conversion.
Hardware Power-Down
The–—H—D—Npin places the converter into the full
power-down mode. Unlike with the software shutdown
modes, conversion is not completed. It stops coinci-
power-up delay if an external reference is used and is
external reference compensation (see Table 7).
Power-Down S equenc ing
The MAX192 auto power-down modes can save con-
siderable power when operating at less than maximum
sample rates. The following discussion illustrates the
various power-down sequences.
Lowest Power at up to 500
Conversions/Channel/Second
The following examples illustrate two different
power-down sequences. Other combinations of clock
rates, compensation modes, and power-down modes
may give lowest power consumption in other applica-
tions.
Table 7. Hard-Wired Shutdown and
Compensation Mode
Table 6. Software Shutdown and Clock Mode
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