參數(shù)資料
型號(hào): MAX1889ETE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 穩(wěn)壓器
英文描述: Triple-Output TFT LCD Power Supply with Fault Protection
中文描述: 2.8 A SWITCHING REGULATOR, 1250 kHz SWITCHING FREQ-MAX, QCC16
封裝: 5 X 5 MM, 0.80 MM HEIGHT, ULTRA THIN, QFN-16
文件頁(yè)數(shù): 24/32頁(yè)
文件大?。?/td> 796K
代理商: MAX1889ETE
M
Triple-Output TFT LCD Power Supply
with Fault Protection
24
______________________________________________________________________________________
Applications Information
PC Board Layout
Careful PC board layout is extremely important for
proper operation. Use the following guidelines for good
PC board layout:
1) Minimize the area of high-current loops by placing
the input capacitors, inductor, output diode, and
output capacitors less than 0.2in (5mm) from the LX
and PGND pins. Connect these components with
traces as wide as possible. Avoid using vias in the
high-current paths. If vias are unavoidable, use
many vias in parallel to reduce resistance and
inductance.
2) Create islands for the analog ground (GND), power
ground (PGND), and linear regulator ground. Star-
connect them to the backside pad of the device.
The REF bypass capacitor and both feedback
dividers should be connected to the analog ground
island (GND). The step-up regulator
s input and out-
put capacitors, and the charge-pump components
should be a wide power ground plane. The power
ground plane should be connected to the power
ground pin (PGND) with a wide trace. Maximizing
the width of the power ground traces improves effi-
ciency and reduces output voltage ripple and noise
spikes. All the other ground connections, such as
the IN pin bypass capacitor and the linear regulator
output capacitors, should be star-connected to the
backside of the device with wide traces. Make no
other connections between these separate ground
planes.
3) Place IN pin and REF pin bypass capacitors as
close to the device as possible.
4) Place all feedback voltage-divider resistors as close
to their respective feedback pins as possible. The
divider
s center trace should be kept short. Placing
the resistors far away causes their FB traces to
become antennas that can pick up switching noise.
Care should be taken to avoid running any feedback
trace near LX or the switching nodes in the charge
pumps.
5) Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
6) Minimize the size of LX node while keeping it wide
and short. Keep the LX node away from feedback
nodes (FB, FBP, and FBN) and analog ground. Use
DC traces as shield if necessary.
Refer to the MAX1889 evaluation kit for an example of
proper board layout.
DRVP
FBP
DRVN
FBN
Q1
Q2
V
PL
7
6
8
9
REF
V
NL
V
N
V
P
MAX1889
C19
1000pF
R9
150k
1%
R8
3k
R10
24.3k
1%
R13
20k
1%
R12
301k
1%
C21
1000pF
R11
3k
Figure 8. LDO Compensation
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