參數(shù)資料
型號(hào): MAX1889ETE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 穩(wěn)壓器
英文描述: Triple-Output TFT LCD Power Supply with Fault Protection
中文描述: 2.8 A SWITCHING REGULATOR, 1250 kHz SWITCHING FREQ-MAX, QCC16
封裝: 5 X 5 MM, 0.80 MM HEIGHT, ULTRA THIN, QFN-16
文件頁(yè)數(shù): 23/32頁(yè)
文件大?。?/td> 796K
代理商: MAX1889ETE
M
Triple-Output TFT LCD Power Supply
with Fault Protection
______________________________________________________________________________________________________
23
To avoid excessive voltage coupling, a small capacitor
can be added in parallel with the base resistor. The
resulting RC time constant should be between 5μs to
50μs.
Stability Requirements
The MAX1889 linear-regulator controllers use an inter-
nal transconductance amplifier to drive an external
pass transistor. The transconductance amplifier, the
pass transistor, the base-emitter resistor, and the out-
put capacitor determine the loop stability. If the output
capacitor and pass transistor are not properly selected,
the linear regulator can be unstable.
The transconductance amplifier regulates the output
voltage by controlling the pass transistor
s base cur-
rent. The total DC loop gain is approximately:
where V
T
is 26mV at room temperature, and I
BIAS
is the
current through the base-to-emitter resistor (R
BE
). This
bias resistor is typically 3k
, providing 0.23mA of cur-
rent, biasing the LDO near its regulation voltage setpoint.
The output capacitor and the load resistance create the
dominant pole in the system. The pass transistor
s input
capacitance creates a second pole in the system.
Additionally, the output capacitor
s ESR generates a zero.
To achieve stable operation, use the following equations
to verify that the linear regulator is properly compensated:
1) First, determine the dominant pole set by the linear
regulator
s output capacitor and the load resistor:
The unity gain crossover of the linear regulator is:
f
CROSSOVER
= A
V(LDO)
f
POLE(CLDO)
2) Next, determine the second pole set by the base-
to-emitter capacitance (including the transistor
s
input capacitance), the transistor
s input resistance,
and the base-to-emitter pullup resistor:
3) A third pole is set by the linear regulator
s feedback
resistance and the capacitance (including stray
capacitance) between FB_ and GND (for the posi-
tive LDO) and FBN and GND (for the negative LDO)
(Figure 8):
4) If the second and third poles occur well after unity-
gain crossover, the linear regulator remains stable:
However, if the ESR zero occurs before the unity-gain
crossover, cancel the zero with the feedback pole by
changing circuit components such that:
For most applications where ceramic capacitors are
used, the ESR zero always occurs after the crossover.
A capacitor connected between the output and the
feedback node improves the transient response,
reduces the noise coupled into the feedback loop, and
maintains the correct regulation point (Figure 8).
Output Capacitor Selection
Typically, more output capacitance provides the best
solution, since this also reduces the output voltage drop
immediately after a load transient. Connect at least a
0.1μF capacitor between the linear regulator
s output and
ground, as close to the external pass transistor as possi-
ble. Depending on the selected pass transistor, larger
capacitor values may be required for stability (see the
Stability Requirements
section). Furthermore, the output
capacitor
s ESR affects stability. Use output capacitors
with an ESR less than 200m
to ensure stability and opti-
mum transient response. Once the minimum capacitor
value for stability is determined, verify that the linear regu-
lator
s output does not contain excessive noise. Although
adequate for stability, small capacitor values can provide
too much bandwidth, making the linear regulator sensitive
to noise. Larger capacitor values reduce the bandwidth,
thereby reducing the regulator
s noise sensitivity. If noise
on the ground reference causes the design to be margin-
ally stable for the negative linear regulator, bypass the
negative output back to its reference voltage. This tech-
nique reduces the differential noise on the output.
f
C
POLE FB
OUT ESR
(
)
1
2
π
f
f
A
POLE CBE
POLE CLDO
(
V LDO
(
(
)
)
)
>
2
f
C
R
(
1
II R
f
C
R II R
(
9
POLE FB
POS
FB
POLE FB
NEG
FB
(
)_
(
)_
)
)
=
=
1
2
12
13
2
10
π
π
f
C
R
(
II R
V h
R
2
C
POLE CBE
BE
BE
IN
BE LOAD
BE BE T FE
π
(
)
)
=
=
+
1
2
π
f
C
I
C
POLE CLDO
(
LDO LOAD
LOAD MAX
π
LDO LDO
)
(
)
=
=
1
2
2
π
A
V
I
I
V
V LDO
(
T
BIAS FE
LOAD
REF
)
.
=
+
5 5
1
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