參數(shù)資料
型號(hào): MAX1403EVL11
廠商: Maxim Integrated Products
文件頁數(shù): 35/36頁
文件大?。?/td> 0K
描述: EVAL KIT FOR MAX1403
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 18
采樣率(每秒): 480
數(shù)據(jù)接口: 串行
輸入范圍: ±VREF/增益
在以下條件下的電源(標(biāo)準(zhǔn)): 16.9mW @ 480SPS
工作溫度: 0°C ~ 70°C
已用 IC / 零件: MAX1403
已供物品: 2 板,CD
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
8
_______________________________________________________________________________________
Note 20: All input signals are specified with tr = tf = 5ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
Note 21: See Figure 4.
Note 22: Timings shown in tables are for the case where SCLK idles high between accesses. The part may also be used with SCLK
idling low between accesses, provided CS is toggled. In this case SCLK in the timing diagrams should be inverted and
the terms “SCLK Falling Edge” and “SCLK Rising Edge” exchanged in the specification tables. If CS is permanently tied
low, the part should only be operated with SCLK idling high between accesses.
Note 23: CLKIN duty cycle range is 45% to 55%. CLKIN must be supplied whenever the MAX1403 is not in standby mode. If no
clock is present, the device can draw higher current than specified.
Note 24: The MAX1403 is production tested with fCLKIN at 2.5MHz (1MHz for some IDD tests).
Note 25: Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits.
Note 26: For read operations, SCLK active edge is falling edge of SCLK.
Note 27: Derived from the time taken by the data output to change 0.5V when loaded with the circuit of Figure 1. The number is
then extrapolated back to remove effects of charging or discharging the 50pF capacitor. This ensures that the times quot-
ed in the timing characteristics are true bus-relinquish times and are independent of external bus loading capacitances.
Note 28: INT returns high after the first read after an output update. The same data can be read again while INT is high, but be
careful not to allow subsequent reads to occur close to the next output update.
Note 29: Auxiliary inputs DS0 and DS1 are latched on the first falling edge of SCLK during a data-read cycle.
SCLK High Pulse Width
t16
100
ns
SCLK Low Pulse Width
t17
100
ns
Data Valid to SCLK Rising Edge
Hold Time
t15
0
ns
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CS Falling Edge to SCLK Falling
Edge Setup Time
t13
30
ns
Data Valid to SCLK Rising Edge
Setup Time
t14
30
ns
CONDITIONS
TIMING CHARACTERISTICS (continued)
(V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, AGND = DGND, fCLKIN = 2.4576MHz, input logic 0 = 0V, logic 1 = VDD, TA = TMIN to
TMAX, unless otherwise noted.) (Notes 20, 21, 22)
CS Rising Edge to SCLK Rising
Edge Hold Time
t18
0
ns
DS0/DS1 to SCLK Falling Edge
Hold Time (Notes 21, 29)
t20
0
ns
DS0/DS1 to SCLK Falling Edge
Setup Time (Notes 21, 29)
t19
40
ns
100
A
at VDD = +3.3V
TO
OUTPUT
PIN
50pF
100
A
at VDD = +3.3V
Figure 1. Load Circuit for Bus-Relinquish Time and VOL and
VOH Levels
AUXILIARY DIGITAL INPUTS (DS0 and DS1)
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參數(shù)描述
MAX1403EVSYSTEM 制造商:Maxim Integrated Products 功能描述:EVALUATION SYSTEM FOR THE MAX1403 - Boxed Product (Development Kits)
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MAX1406CAE 功能描述:RS-232接口集成電路 RoHS:否 制造商:Exar 數(shù)據(jù)速率:52 Mbps 工作電源電壓:5 V 電源電流:300 mA 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:LQFP-100 封裝:
MAX1406CAE+ 功能描述:RS-232接口集成電路 15kV ESD-Protected 230kbps RS-232 LD/Rc RoHS:否 制造商:Exar 數(shù)據(jù)速率:52 Mbps 工作電源電壓:5 V 電源電流:300 mA 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:LQFP-100 封裝:
MAX1406CAE+T 功能描述:RS-232接口集成電路 15kV ESD-Protected 230kbps RS-232 LD/Rc RoHS:否 制造商:Exar 數(shù)據(jù)速率:52 Mbps 工作電源電壓:5 V 電源電流:300 mA 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:LQFP-100 封裝: