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參數(shù)資料
| 型號： | MAX1303BEUP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 17/29頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT MULT RANGE 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 115k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 105.5mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，雙極 |
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Full Power-Down Mode (Mode 7)
When M[2:0] = 111, the device enters full power-down
mode and the total supply current falls to 1A (typ). In full
power-down, all analog portions of the device are powered
down. When using the internal reference, upon exiting full
power-down mode, allow 10ms for the internal reference
voltage to stabilize prior to initiating a conversion.
To exit full power-down, change the mode by issuing
one of the following mode-control bytes (see the
Mode
Control section):
External-clock-mode control byte
External-acquisition-mode control byte
Internal-clock-mode control byte
Reset byte
Partial power-down-mode control byte
This prevents the MAX1303 from inadvertently exiting
full power-down mode because of a CS glitch in a noisy
digital environment.
Power-On Reset
The MAX1303 powers up in normal operation config-
ured for external clock mode with all circuitry active
(Tables 7 and 8). Each analog input channel
(CH0–CH7) is set for single-ended conversions with a
±VREF bipolar input range (Table 6).
Allow the power supplies to stabilize after power-up. Do
not initiate any conversions until the power supplies
have stabilized. Additionally, allow 10ms for the internal
reference to stabilize when CREF = 1.0F and CRECAP
= 0.1F. Larger reference capacitors require longer
stabilization times.
Internal or External Reference
The MAX1303 operates with either an internal or external
reference. The reference voltage impacts the ADC’s FSR
(Figures 11, 12, and 13). An external reference is recom-
mended if more accuracy is required than the internal ref-
erence provides, and/or multiple converters require the
same reference voltage.
Internal Reference
The MAX1303 contains an internal 4.096V bandgap refer-
ence. This bandgap reference is connected to REFCAP
through a nominal 5k
resistor (Figure 16). The voltage at
REFCAP is buffered creating 4.096V at REF. When using
the internal reference, bypass REFCAP with a 0.1F or
greater capacitor to AGND1 and bypass REF with a
1.0F or greater capacitor to AGND1.
External Reference
For external reference operation, disable the internal
reference and reference buffer by connecting REFCAP
to AVDD1. With AVDD1 connected to REFCAP, REF
becomes a high-impedance input and accepts an
external reference voltage. The MAX1303 external ref-
erence current varies depending on the applied refer-
ence voltage and the operating mode (see the External
Reference Input Current vs. External Reference Input
Voltage in the
Typical Operating Characteristics).
MAX1303
4-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
24
______________________________________________________________________________________
REF
REFCAP
AGND1
4.096V
BANDGAP
REFERENCE
5k
1x
SAR
ADC REF
4.096V
1.0
F
0.1
F
VRCTH
MAX1303
Figure 16. Internal Reference Operation
M2
M1
M0
MODE
0
External Clock (DEFAULT)
0
1
External Acquisition
0
1
0
Internal Clock
0
1
Reserved
1
0
Reset
1
0
1
Reserved
1
0
Partial Power-Down
1
Full Power-Down
Table 8. Mode-Control Bits M[2:0]
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