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參數(shù)資料
| 型號： | MAX1303BEUP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT MULT RANGE 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 115k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 105.5mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，雙極 |
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External Acquisition Mode (Mode 1)
The slowest maximum throughput rate is achieved with
the external acquisition method. SCLK controls the
acquisition of the analog signal in external acquisition
mode, facilitating precise control over when the analog
signal is captured. The internal clock controls the con-
version of the analog input voltage. The analog input
sampling instant is at the falling edge of the 16th SCLK
(Figure 2).
For the external acquisition mode, CS must remain low
for the first 15 clock cycles and then rise on or after the
falling edge of the 16th SCLK cycle as shown in Figure
2. For optimal performance, idle DIN and SCLK during
the conversion. With careful board layout, transitions at
DIN and SCLK during the conversion have a minimal
impact on the conversion result.
After the conversion is complete, SSTRB asserts high
and CS can be brought low to read the conversion
result. SSTRB returns low on the rising SCLK edge of
the subsequent start bit.
Internal Clock Mode (Mode 2)
In internal clock mode, the internal clock controls both
acquisition and conversion of the analog signal. The inter-
nal clock starts approximately 100ns to 400ns after the
falling edge of the eighth SCLK and has a rate of about
4.5MHz. The analog input sampling instant occurs at the
falling edge of the 11th internal clock signal (Figure 3).
For the internal clock mode, CS must remain low for the
first seven SCLK cycles and then rise on or after the
falling edge of the eighth SCLK cycle. After the conver-
sion is complete, SSTRB asserts high and CS can be
brought low to read the conversion result. SSTRB returns
low on the rising SCLK edge of the subsequent start bit.
Reset (Mode 4)
As shown in Table 8, set M[2:0] = 100 to reset the
MAX1303 to its default conditions. The default condi-
tions are full power operation with each channel config-
ured for ±VREF, bipolar, single-ended conversions
using external clock mode (mode 0).
Partial Power-Down Mode (Mode 6)
As shown in Table 8, when M[2:0] = 110, the device enters
partial power-down mode. In partial power-down, all ana-
log portions of the device are powered down except for the
reference voltage generator and bias supplies.
To exit partial power-down, change the mode by issu-
ing one of the following mode-control bytes (see the
Mode Control section):
External-clock-mode control byte
External-acquisition-mode control byte
Internal-clock-mode control byte
Reset byte
Full power-down-mode control byte
This prevents the MAX1303 from inadvertently exiting
partial power-down mode because of a CS glitch in a
noisy digital environment.
MAX1303
4-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
______________________________________________________________________________________
23
CS
SCLK
DIN
DOUT
18
START
SEL2
SEL1
SEL0
R2
R1
R0
DIF/SGL
tCL
tCP
tCH
tDV
tCSS
tDS
tDH
tCSH
tCSPW
tTR
HIGH
IMPEDANCE
18
START
M2
M1
M0
1
0
ANALOG INPUT CONFIGURATION BYTE
MODE CONTROL BYTE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 14. Analog Input Configuration Byte and Mode-Control Byte Timing
CS
SCLK
DOUT
tCSS
HIGH IMPEDANCE
SSTRB
tSSCS
MSB
tDO
NOTE: SSTRB AND CS REMAIN LOW IN EXTERNAL CLOCK MODE (MODE 0).
Figure 15. DOUT and SSTRB Timing
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