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參數(shù)資料
| 型號： | MAX1303BEUP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 15/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT MULT RANGE 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 115k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 105.5mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，雙極 |
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Mode Control
The MAX1303 contains one byte-wide mode-control
register. The timing diagram of Figure 14 shows how to
use the mode-control byte, and the mode-control byte
format is shown in Table 7. The mode-control byte is
used to select the conversion method and to control the
power modes of the MAX1303.
Selecting the Conversion Method
The conversion method is selected using the mode-con-
trol byte (see the
Mode Control section), and the conver-
sion is initiated using a conversion start command (Table
3, and Figures 1, 2, and 3).The MAX1303 converts ana-
log signals to digital data using one of three methods:
External Clock Mode, Mode 0 (Figure 1)
Highest maximum throughput (see the
Electrical
Characteristics table)
User controls the sample instant
CS remains low during the conversion
User supplies SCLK throughout the ADC con-
version and reads data at DOUT
External Acquisition Mode, Mode 1 (Figure 2)
Lowest maximum throughput (see the
Electrical
Characteristics table)
User controls the sample instant
User supplies two bytes of SCLK, then drives
CS high to relieve processor load while the
ADC converts
After SSTRB transitions high, the user supplies
two bytes of SCLK and reads data at DOUT
Internal Clock Mode, Mode 2 (Figure 3)
High maximum throughput (see the
Electrical
Characteristics table)
The internal clock controls the sampling instant
User supplies one byte of SCLK, then drives CS
high to relieve processor load while the ADC
converts
After SSTRB transitions high, the user supplies
two bytes of SCLK and reads data at DOUT
External Clock Mode (Mode 0)
The MAX1303’s fastest maximum throughput rate is
achieved operating in external clock mode. SCLK con-
trols both the acquisition and conversion of the analog
signal, facilitating precise control over when the analog
signal is captured. The analog input sampling instant is
at the falling edge of the 14th SCLK (Figure 1).
Since SCLK drives the conversion in external clock
mode, the SCLK frequency should remain constant
while the conversion is clocked. The minimum SCLK
frequency prevents droop in the internal sampling
capacitor voltages during conversion.
SSTRB remains low in the external clock mode, and as a
result may be left unconnected if the MAX1303 will
always be used in the external clock mode.
MAX1303
4-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
22
______________________________________________________________________________________
Table 7. Mode-Control Byte
BIT NUMBER
BIT NAME
DESCRIPTION
7
START
Start Bit. The first logic 1 after CS goes low defines the beginning of the mode-control byte.
6M2
5M1
4M0
Mode-Control Bits. M[2:0] select the mode of operation as shown in Table 8.
3
1
Bit 3 must be a logic 1 for the mode-control byte.
2
0
Bit 2 must be a logic 0 for the mode-control byte.
1
0
Bit 1 must be a logic 0 for the mode-control byte.
0
Bit 0 must be a logic 0 for the mode-control byte.
1 LSB =
FSR x VREF
65,536 x 4.096V
BINARY
OUTPUT
CODE
(LSB
[hex])
FFFF
FFFE
FFFD
8001
8000
7FFF
0003
0002
0001
0000
FSR
0
1
2
3
32,768
65,533 65,535
INPUT VOLTAGE (LSB [DECIMAL])
(AGND1)
FSR
Figure 13. Ideal Unipolar Transfer Function, Single-Ended
Input, 0 to +FSR
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