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參數(shù)資料
| 型號： | MAX1221BETX+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 31/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC/DAC 12BIT W/FIFO 36TQFNEP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | ADC，DAC |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 225k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 2.7 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 36-TQFN 裸露焊盤（6x6） |
| 包裝： | 帶卷 (TR) |
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MAX1221/MAX1223/MAX1343
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________
37
tCSH
SCLK
DIN
DOUT
CS
12
3
4
32
16
8
D15
D14
D13
D12
D11
5
D15
D7
D14
D6
D13
D5
D12
D4
D0
D1
D0
tDOD
tDOT
tCSS
tCSPWH
D1
tDOE
tDS
tDH
tCH
tCL
Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10)
nAVG = samples per result (amount of averaging)
nSCAN = number of times each channel is scanned; set
to one unless [SCAN1, SCAN0] = 10
tTS = time required for temperature measurement
(58.1s); set to zero if temperature measurement is not
requested
tINT-REF,SU = tWU (external-reference wake-up); if a
conversion using the external reference is requested
In clock mode 01, the total conversion time depends on
how long
CNVST is held low or high. Conversion time in
externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long
CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
DAC/GPIO Timing
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing speci-
fications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware
LDAC command DAC-
register update. For a software-command DAC-register
update, tS is valid from the rising edge of CS, which fol-
lows the last data bit in the software command word.
LDAC Functionality
Drive
LDAC low to transfer the content of the input reg-
isters to the DAC registers. Drive
LDAC permanently
low to make the DAC register transparent. The DAC
output typically settles from zero to full scale within ±1
LSB after 2s. See Figure 14.
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