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參數(shù)資料
| 型號(hào)： | MAX1221BETX+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 28/44頁 |
| 文件大小： | 0K |
| 描述： | IC ADC/DAC 12BIT W/FIFO 36TQFNEP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | ADC，DAC |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 225k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 2.7 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 36-TQFN 裸露焊盤（6x6） |
| 包裝： | 帶卷 (TR) |
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MAX1221/MAX1223/MAX1343
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
34
______________________________________________________________________________________
Applications Information
Internally Timed Acquisitions and
Conversions Using CNVST
ADC Conversions in Clock Mode 00
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequence is initiated through
CNVST
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 6 for clock mode 00 timing after a
command byte is issued. See Table 5 for details on
programming the clock mode in the setup register.
Initiate a scan by setting
CNVST low for at least 40ns
before pulling it high again. The MAX1221/MAX1223/
MAX1343 then wake up, scan all requested channels,
store the results in the FIFO, and shut down. After the
scan is complete,
EOC is pulled low and the results are
available in the FIFO. Wait until
EOC goes low before
pulling
CS low to communicate with the serial interface.
EOC stays low until CS or CNVST is pulled low again. A
temperature-conversion result, if requested, precedes
all other FIFO results.
Do not issue a second
CNVST signal before EOC goes
low; otherwise, the FIFO can be corrupted. Wait until all
conversions are complete before reading the FIFO. SPI
communications to the DAC and GPIO registers are per-
mitted during conversion. However, coupled noise may
result in degraded ADC signal-to-noise ratio (SNR).
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
DOUT
MSB1
tRDS
LSB1
MSB2
SCLK
CNVST
EOC
Figure 6. Clock Mode 00—After writing a command byte, set
CNVST low for at least 40ns to begin a conversion.
(CONVERSION 2)
tCSW
tDOV
(ACQUISITION 2)
(ACQUISITION 1)
(CONVERSION 1)
CS
DOUT
MSB1
LSB1
MSB2
SCLK
CNVST
EOC
Figure 7. Clock Mode 01—After writing a command byte, request multiple conversions by setting
CNVST low for each conversion.
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