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參數(shù)資料
| 型號： | MAX1221BETX+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 24/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC/DAC 12BIT W/FIFO 36TQFNEP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | ADC，DAC |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 225k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 2.7 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 36-TQFN 裸露焊盤（6x6） |
| 包裝： | 帶卷 (TR) |
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MAX1221/MAX1223/MAX1343
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
30
______________________________________________________________________________________
Table 13. MAX1221/MAX1343 GPIO Configuration
DATA PIN
GPIO COMMAND BYTE
DATA BYTE
DIN
0
1
GPIOC1
GPIOC0
GPIOA1
GPIOA0
X
DOUT
0
0000
Table 14. MAX1221/MAX1343 GPIO Write
DATA PIN
GPIO COMMAND BYTE
DATA BYTE
DIN
0
1
0
GPIOC1
GPIOC0
GPIOA1
GPIOA0
X
DOUT
00
000
00
0
GPIO Command
Write a command byte to the GPIO command register
to configure, write, or read the GPIOs, as detailed in
Table 12.
Write the command byte 00000011 to configure the
GPIOs. The eight SCLK cycles following the command
byte load data from DIN to the GPIO configuration reg-
ister in the MAX1221/MAX1343. See Tables 13 and 14.
The register bits are updated after the last
CS rising
edge. All GPIOs default to inputs upon power-up.
The data in the register controls the function of each
GPIO, as shown in Tables 13, 14, and 16.
GPIO Write
Write the command byte 00000010 to indicate a GPIO
write operation. The eight SCLK cycles following the com-
mand byte load data from DIN into the GPIO write register
in the MAX1221/MAX1343. See Tables 14 and 15. The
register bits are updated after the last
CS rising edge.
GPIO Read
Write the command byte 00000001 to indicate a GPIO
read operation. The eight SCLK cycles following the
command byte transfer the state of the GPIOs to DOUT
in the MAX1221/MAX1343. See Table 16.
DAC Serial Interface
Write a command byte 0001XXXX to the DAC select
register to indicate the word to follow is written to the
DAC serial interface, as detailed in Tables 1, 10, 17, and
18. Write the next 16 bits to the DAC interface register,
as shown in Tables 17 and 18. Following the high-to-low
transition of
CS, the data is shifted synchronously and
latched into the input register on each falling edge of
SCLK. Each word is 16 bits. The first 4 bits are the con-
trol bits followed by 12 data bits (MSB first). See Figures
9–12 for DAC timing specifications.
If
CS goes high prior to completing 16 SCLK cycles, the
command is discarded. To initiate a new transfer, drive
CS low again.
For example, writing the DAC serial interface word 1111
0000 and 0011 0100 disconnects DAC outputs 2 and 3
Table 15. GPIO-Mode Control
CONFIGURATION
BIT
WRITE
BIT
OUTPUT
STATE
GPIO
FUNCTION
1
Output
1
0
Output
0
1
Tri-state
Input
00
0
Pulldown
(open drain)
Table 16. MAX1221/MAX1343 GPIO Read
DATA PIN
GPIO COMMAND BYTE
DATA BYTE
DIN
00
000001
X
DOUT
00
000000
0
GPIOC1
GPIOC0
GPIOA1
GPIOA0
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