參數資料
型號： MAX1221BETX+T
廠商： Maxim Integrated Products
文件頁數： 29/44頁
文件大?。?/td> 0K
描述： IC ADC/DAC 12BIT W/FIFO 36TQFNEP
產品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
類型： ADC，DAC
分辨率（位）： 12 b
采樣率（每秒）： 225k
數據接口： MICROWIRE?，QSPI?，串行，SPI?
電壓電源： 模擬和數字
電源電壓： 2.7 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 36-WFQFN 裸露焊盤
供應商設備封裝： 36-TQFN 裸露焊盤（6x6）
包裝： 帶卷 (TR)
MAX1221/MAX1223/MAX1343
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________
35
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
MSB1
tDOV
LSB1
MSB2
(CONVERSION BYTE)
CS
DOUT
SCLK
DIN
EOC
Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (
CNVST is not required).
Externally Timed Acquisitions and
Internally Timed Conversions with CNVST
ADC Conversions in Clock Mode 01
In clock mode 01, conversions are requested one at a
time using
CNVST and performed automatically using
the internal oscillator. See Figure 7 for clock mode 01
timing after a command byte is issued.
Setting
CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold
CNVST low for
at least 1.4s to complete the acquisition. If reference
mode 00 or 10 is selected, an additional 45s is
required for the internal reference to power up. If a tem-
perature measurement is being requested, reference
power-up and temperature measurement is internally
timed. In this case, hold
CNVST low for at least 40ns.
Set
CNVST high to begin a conversion. Sampling is
completed approximately 500ns after
CNVST goes high.
After the conversion is complete, the ADC shuts down
and pulls
EOC low. EOC stays low until CS or CNVST is
pulled low again. Wait until
EOC goes low before pulling
CS or CNVST low. The number of CNVST signals must
equal the number of conversions requested by the scan
and averaging registers to correctly update the FIFO.
Wait until all conversions are complete before reading
the FIFO. SPI communications to the DAC and GPIO
registers are permitted during conversion. However,
coupled noise may result in degraded ADC SNR.
If averaging is turned on, multiple
CNVST pulses need to
be performed before a result is written to the FIFO. Once
the proper number of conversions has been performed
to generate an averaged FIFO result (as specified to the
averaging register), the scan logic automatically switch-
es the analog input multiplexer to the next requested
channel. If a temperature measurement is programmed,
it is performed after the first rising edge of
CNVST follow-
ing the command byte written to the conversion register.
The temperature-conversion result is available on DOUT
once
EOC has been pulled low.
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