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參數資料
| 型號： | MAX1162EVKIT |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 6/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL KIT FOR MAX1162 |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| ADC 的數量： | 1 |
| 位數： | 16 |
| 采樣率（每秒）： | 200k |
| 數據接口： | 串行 |
| 輸入范圍： | 0 ~ VREF |
| 在以下條件下的電源（標準）： | 12.5mW @ 200kSPS |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | MAX1162，MAX1062 |
| 已供物品： | 板，CD |
MAX1162
16-Bit, +5V, 200ksps ADC with 10A
Shutdown
14
______________________________________________________________________________________
PIC16 with SSP Module and
PIC17 Interface
The MAX1162 is compatible with a PIC16/PIC17 micro-
controller (C) using the synchronous serial-port (SSP)
module.
To establish SPI communication, connect the controller
as shown in Figure 12a. Configure the PIC16/PIC17 as
system master, by initializing its synchronous serial-port
control register (SSPCON) and synchronous serial-port
status register (SSPSTAT) to the bit patterns shown in
Tables 1 and 2.
In SPI mode, the PIC16/PIC17 C allows 8 bits of data
to be synchronously transmitted and received simulta-
CS
QSPI
SCLK
DOUT
CS
SCK
MISO
VDD
SS
MAX1162
SCK
SDI
GND
PIC16/17
I/O
SCLK
DOUT
CS
VDD
MAX1162
Figure 11a. QSPI Connections
Figure 12a. SPI Interface Connection for a PIC16/PIC17
DOUT*
CS
SCLK
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
20
16
D15
D14
D13
D12
D11
D10
D9
HIGH-Z
D1
D0
24
12
14
8
6
D8
D5
D4
D3
LSB
D7
D6
END OF
ACQUISITION
D2
Figure 11b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
CONTROL BIT
MAX1162
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL
BIT7
X
Write Collision Detection Bit
SSPOV
BIT6
X
Receive Overflow Detect Bit
SSPEN
BIT5
1
Synchronous Serial-Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
CKP
BIT4
0
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3
BIT3
0
SSPM2
BIT2
0
SSPM1
BIT1
0
SSPM0
BIT0
1
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects
fCLK = fOSC / 16.
Table 1. Detailed SSPCON Register Contents
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