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參數(shù)資料
| 型號： | MAX1162EVKIT |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 18/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL KIT FOR MAX1162 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ VREF |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 12.5mW @ 200kSPS |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | MAX1162，MAX1062 |
| 已供物品： | 板，CD |
MAX1162
16-Bit, +5V, 200ksps ADC with 10A
Shutdown
_______________________________________________________________________________________
9
Input Bandwidth
The ADC’s input tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use anti-alias filtering.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to AVDD or AGND, allow the input to swing from
AGND - 0.3V to AVDD + 0.3V, without damaging the
device.
If the analog input exceeds 300mV beyond the sup-
plies, limit the input current to 10mA.
SCLK
DOUT
tCSS
tCH
tCL
tDV
tCSH
tCSW
tTR
tDO
tCP
CS
TIMING NOT TO SCALE.
Figure 3. Detailed Serial Interface Timing
SCLK
DOUT
AGND
DGND
AIN
REF
AVDD
DVDD
DOUT
SCLK
CS
AIN
VREF
+5V
4.7
F
0.1
F
0.1
F
GND
MAX1162
CS
Figure 4. Typical Operating Circuit
DOUT
a) VOL TO VOH
b) HIGH-Z TO VOL AND VOH TO VOL
DOUT
1mA
DGND
CLOAD = 50pF
VDD
Figure 1. Load Circuits for DOUT Enable Time and SCLK to
DOUT Delay Time
DOUT
a) VOH TO HIGH-Z
b) VOL TO HIGH-Z
DOUT
1mA
DGND
CLOAD = 50pF
VDD
Figure 2. Load Circuits for DOUT Disable Time
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