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參數(shù)資料
| 型號(hào)： | MAX1162EVKIT |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/18頁 |
| 文件大小： | 0K |
| 描述： | EVAL KIT FOR MAX1162 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ VREF |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 12.5mW @ 200kSPS |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | MAX1162，MAX1062 |
| 已供物品： | 板，CD |
MAX1162
16-Bit, +5V, 200ksps ADC with 10A
Shutdown
______________________________________________________________________________________
11
Output Coding and
Transfer Function
The data output from the MAX1162 is binary and Figure
8 depicts the nominal transfer function. Code transitions
occur halfway between successive-integer LSB values
(VREF = 4.096V and 1LSB = 63V or 4.096V/65536).
Applications Information
External Reference
The MAX1162 requires an external reference with a
+3.8V and AVDD voltage range. Connect the external
reference directly to REF. Bypass REF to AGND (pin 3)
with a 4.7F capacitor. When not using a low-ESR
bypass capacitor, use a 0.1F ceramic capacitor in
parallel with the 4.7F capacitor. Noise on the refer-
ence degrades conversion accuracy.
The input impedance at REF is 40k
for DC currents.
During a conversion the external reference at REF must
deliver 100A of DC load current and have an output
impedance of 10
or less.
For optimal performance, buffer the reference through
an op amp and bypass the REF input. Consider the
MAX1162’s equivalent input noise (38VRMS) when
choosing a reference.
Input Buffer
Most applications require an input buffer amplifier to
achieve 16-bit accuracy. If the input signal is multi-
plexed, switch the input channel immediately after acqui-
sition, rather than near the end of or after a conversion
(Figure 9). This allows the maximum time for the input
buffer amplifier to respond to a large step change in the
input signal. The input amplifier must have a slew rate of
at least 2V/s to complete the required output-voltage
change before the beginning of the acquisition time.
At the beginning of the acquisition, the internal sampling
capacitor array connects to AIN (the amplifier output),
causing some output disturbance. Ensure that the sampled
voltage has settled before the end of the acquisition time.
Digital Noise
Digital noise can couple to AIN and REF. The conver-
sion clock (SCLK) and other digital signals active dur-
ing input acquisition contribute noise to the conversion
result. Noise signals synchronous with the sampling
interval result in an effective input offset. Asynchronous
signals produce random noise on the input, whose
high-frequency components can be aliased into the fre-
COMPLETE CONVERSION SEQUENCE
CONVERSION 0
CONVERSION 1
POWERED UP
POWERED DOWN
DOUT
CS
TIMING NOT TO SCALE.
Figure 7. Shutdown Sequence
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
12
3
0
FS
FS - 3/2LSB
FS = VREF
INPUT VOLTAGE (LSB)
1LSB =
VREF
65536
Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF,
Zero Scale (ZS) = GND
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