- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17009 > MAX1162EVKIT (Maxim Integrated Products)EVAL KIT FOR MAX1162 PDF資料下載
參數(shù)資料
| 型號： | MAX1162EVKIT |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL KIT FOR MAX1162 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ VREF |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 12.5mW @ 200kSPS |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | MAX1162，MAX1062 |
| 已供物品： | 板，CD |
MAX1162
16-Bit, +5V, 200ksps ADC with 10A
Shutdown
______________________________________________________________________________________
13
format. Observe the SCLK to DOUT valid timing
characteristic. Clock data into the P on SCLK’s ris-
ing edge.
3) Pull CS high at or after the 24th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the least significant bit (D0 = LSB).
4) With CS high, wait at least 50ns (tCSW) before start-
ing a new conversion by pulling CS low. A conver-
sion can be aborted by pulling CS high before the
conversion ends. Wait at least 50ns before starting a
new conversion.
Data can be output in three 8-bit sequences or continu-
ously. The bytes contain the results of the conversion
padded with eight leading zeros before the MSB. If the
serial clock has not been idled after the LSB (D0) and
CS has been kept low, DOUT sends trailing zeros.
SPI and MICROWIRE Interfaces
When using the SPI (Figure 10a) or MICROWIRE
(Figure 10b) interfaces, set CPOL = 0 and CPHA = 0.
Conversion begins with a falling edge on CS (Figure
10c). Three consecutive 8-bit readings are necessary
to obtain the entire 16-bit result from the ADC. DOUT
data transitions on the serial clock’s falling edge. The
first 8-bit data stream contains all leading zeros. The
second 8-bit data stream contains the MSB through D8.
The third 8-bit data stream contains D7 through D0.
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX1162 supports a maximum
fSCLK of 4.8MHz. Figure 11a shows the MAX1162 con-
nected to a QSPI master and Figure 11b shows the
associated interface timing.
CS
SCLK
DOUT
I/O
SCK
MISO
SPI
VDD
SS
MAX1162
Figure 10a. SPI Connections
MAX1162
CS
MICROWIRE
SCLK
DOUT
I/O
SK
SI
Figure 10b. MICROWIRE Connections
DOUT*
CS
SCLK
1ST BYTE READ
2ND BYTE READ
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
HIGH-Z
3RD BYTE READ
LSB
D1
D0
D7
D6
D5
D4
D3
D2
24
20
16
12
8
6
4
1
D15
D14
D13
D12
D11
D10
D9
D8
D7
0
00
0
TIMING NOT TO SCALE.
Figure 10c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-22Y-EW | CONVERTER MOD DC/DC 3.3V 66W |
| 1301540056 | CORD Y-SPLICE 1-2447 & 2-2547 |
| HFI-160808-1N2S | INDUCTOR 1.6X0.8X0.8MM 1.2NH |
| RCB13DHHN | CONN EDGECARD 26POS DIP .050 SLD |
| MAX1294EVKIT | EVALUATION KIT FOR MAX1294 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1162EVSYS | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Evaluation System/Evaluation Kit for the MAX1162/MAX1062 |
| MAX11630EEG+ | 制造商:Maxim Integrated Products 功能描述:12-BIT 300KSPS ADCS WITH FIFO AND INTERNAL REFERENCE - Rail/Tube |
| MAX11630EEG+T | 制造商:Maxim Integrated Products 功能描述:12-BIT 300KSPS ADCS WITH FIFO AND INTERNAL REFERENCE - Tape and Reel |
| MAX11631EEG+ | 制造商:Maxim Integrated Products 功能描述:12-BIT 300KSPS ADCS WITH FIFO AND INTERNAL REFERENCE - Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。