參數(shù)資料
型號(hào)： MAX108CHC
廠(chǎng)商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： ADC
英文描述： 【5V, 1.5Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier
中文描述： 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PBGA192
封裝： 25 X 25 MM, ESBGA-192
文件頁(yè)數(shù)： 5/32頁(yè)
文件大?。?/td> 428K
代理商： MAX108CHC
M
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
_______________________________________________________________________________________
5
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
A = V
CC
I = V
CC
D = +5.0V, V
EE
= -5.0V, V
CC
O = +3.3V, REFIN connected to REFOUT, f
S
= 1.5Gsps, f
IN
at -1dBFS, T
A
= +25°C,
unless otherwise noted.)
DIV4 mode
DIV1, DIV2 modes
7.5
8.5
DIV4 mode
DIV1, DIV2 modes
Figures 6, 7, 8
t
PDP
Auxiliary Port Pipeline
Delay
t
PDA
9.5
Clock
Cycles
Figures 6, 7, 8
DREADY to DATA Propagation
Delay (Note 14)
t
PD2
-50
150
350
ps
Figure 17
CLK to DREADY Propagation
Delay
t
PD1
2.2
ns
Figure 17
Reset Input Data Hold Time
(Note 13)
t
HD
0
ps
Figure 15
Clock Pulse Width High
Aperture Delay
t
PWH
t
AD
0.3
5
ns
ps
Figure 17
Figure 4
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Aperture Jitter
t
AJ
<0.5
ps
100
Reset Input Data Setup Time
(Note 13)
t
SU
0
ps
DATA Rise Time
DATA Fall Time
DREADY Rise Time
DREADY Fall Time
t
RDATA
t
FDATA
t
RDREADY
t
FDREADY
420
360
220
180
7.5
ps
ps
ps
ps
Maximum Sample Rate
Clock Pulse Width Low
f
MAX
t
PWL
1.5
0.3
Gsps
ns
Primary Port Pipeline
Delay
Clock
Cycles
CONDITIONS
Figure 4
Figure 15
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
Figure 17
TIMING CHARACTERISTICS
Note 1:
Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale
range (FSR) is defined as 256 times the slope of the line.
The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit
voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.
The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings
on the CLK+ and CLK- inputs.
Input logic levels are measured with respect to the V
CC
O power-supply voltage.
All PECL digital outputs are loaded with 50
to V
CC
O - 2.0V. Measurements are made with respect to the V
CC
O power-
supply voltage.
The current in the V
CC
O power supply does not include the current in the digital output’s emitter followers, which is a func-
tion of the load resistance and the V
TT
termination voltage.
Common-mode rejection ratio (CMRR) is defined as the ratio of the change in the transfer-curve offset voltage to the
change in the common-mode voltage, expressed in dB.
Power-supply rejection ratio (PSRR) is defined as the ratio of the change in the transfer-curve offset voltage to the change
in power-supply voltage, expressed in dB.
Measured with the positive supplies tied to the same potential; V
CC
A = V
CC
D = V
CC
I. V
CC
varies from +4.75V to +5.25V.
Note 10:
V
EE
varies from -5.25V to -4.75V.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
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