參數(shù)資料
型號(hào): MAX108CHC
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 【5V, 1.5Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier
中文描述: 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PBGA192
封裝: 25 X 25 MM, ESBGA-192
文件頁數(shù): 12/32頁
文件大小: 428K
代理商: MAX108CHC
M
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
12
______________________________________________________________________________________
_______________Detailed Description
The MAX108 is an 8-bit, 1.5Gsps flash analog-to-digital
converter (ADC) with on-chip T/H amplifier and differ-
ential PECL-compatible outputs. The ADC (Figure 1)
employs a fully differential 8-bit quantizer and a unique
encoding scheme to limit metastable states, with no
error exceeding 1LSB max.
An integrated 8:16 output demultiplexer simplifies inter-
facing to the part by reducing the output data rate to
one-half the sampling clock rate. This demultiplexer
has internal reset capability that allows multiple
MAX108s to be time-interleaved to achieve higher
effective sampling rates.
When clocked at 1.5Gsps, the MAX108 provides a typi-
cal ENOB of 7.5 bits at an analog input frequency of
750MHz. The analog input of the MAX108 is designed
for differential or single-ended use with a ±250mV full-
scale input range. In addition, this fast ADC features an
on-chip +2.5V precision bandgap reference. If desired,
an external reference can also be used.
Figure 1. Simplified Functional Diagram
CLK-
RSTIN+
RSTIN-
VOSADJ
BANDGAP
REFERENCE
+2.5V
CLK+
CLKCOM
VIN-
VIN+
REF
OUT
REF
IN
DEMUXEN DIVSELECT
DEMUX
CLOCK
DRIVER
16
50
50
50
50
RSTOUT
A0–A7
P0–P7
DREADY
OR
DIFFERENTIAL
PECL OUTPUTS
T/H
CLOCK
DRIVER
ADC
CLOCK
DRIVER
REFERENCE
AMPLIFIER
2
2
DEMUX
CLOCK
GENERATOR
RESET
INPUT DUAL LATCH
RESET
PIPELINE
GNDI
GNDI
GNDR
DELAYED
RESET
16
16
2
2
T/H AMPLIFIER
LOGIC
CLOCK
DRIVER
BIAS CURRENTS
OVERRANGE
BIT
AUXILIARY
DATA PORT
PRIMARY
DATA PORT
DATA
READY CLOCK
DEMUX
RESET OUTPUT
8-BIT
FLASH ADC
MAX108
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