參數(shù)資料
型號(hào)： MAX104
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： ADC
英文描述： 【5V, 1Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier
中文描述： 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PGA192
文件頁(yè)數(shù)： 20/32頁(yè)
文件大?。?/td> 637K
代理商： MAX104
M
inputs are AC-coupled. Under this condition, connect
CLKCOM to GNDI. Single-ended ECL/PECL/sine-wave
drive is also possible if the undriven clock input is
reverse-terminated to GNDI through a 50
resistor in
series with a capacitor whose value is identical to that
used to couple the driven input.
Demux Reset Operation
The MAX104 features an internal 1:2 demultiplexer that
reduces the data rate of the output digital data to one-
half the sample clock rate. Demux reset is necessary
when interleaving multiple MAX104s and/or synchroniz-
ing external demultiplexers. The simplified block diagram
of Figure 1 shows that the demux reset signal path con-
sists of four main circuit blocks. From input to output,
they are the reset input dual latch, the reset pipeline, the
demux clock generator, and the reset output. The sig-
nals associated with the demux reset operation and the
control of this section are listed in Table 6.
Reset Input Dual Latch
The reset input dual-latch circuit block accepts differ-
ential PECL reset inputs referenced to the same V
CC
O
power supply that powers the MAX104 PECL outputs.
For applications that do not require a synchronizing
reset, the reset inputs can be left open. In this case,
they will self-bias to a proper level with internal 50k
resistors and 20μA current source. This combination
creates a -1V difference between RSTIN+ and RSTIN-
to disable the internal reset circuitry. When driven with
PECL logic levels terminated with 50
to (V
CC
O - 2V),
the internal biasing network can easily be overdriven.
Figure 14 shows a simplified schematic of the reset
input structure.
To properly latch the reset input data, the setup time
(t
SU
) and the data hold time (t
HD
) must be met with
respect to the rising edge of the sample clock. The tim-
ing diagram of Figure 15 shows the timing relationship
of the reset input and sampling clock.
±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Trac k/Hold Amplifier
20
______________________________________________________________________________________
Table 5. DC-Coupled Clock Drive Options
-10dBm to +4dBm
Figure 13a
Single-Ended Sine Wave
CLK+
GNDI
CLKCOM
CLOCK DRIVE
REFERENCE
External 50
to GNDI
CLK-
-10dBm to +4dBm
-10dBm to +4dBm
Figure 13b
Differential Sine Wave
GNDI
ECL Drive
-1.3V
Figure 13c
Single-Ended ECL
-2V
ECL Drive
ECL
Drive
Figure 13d
Differential ECL
-2V
50k
50k
RSTIN+
RSTIN-
RESET INPUTS ARE
ESD PROTECTED
(NOT SHOWN IN THIS
SIMPLIFIED DRAWING).
20
μ
A
GNDD
V
CC
O
Figure 14. Simplified Reset Input Structure
RSTIN+
50%
50%
CLK+
CLK-
RSTIN-
50%
t
SU
t
HD
Figure 15. Reset Input Timing Definitions
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參數(shù)描述
MAX1040 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports
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MAX1040BETX 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX1040BETX+ 功能描述:ADC / DAC多通道 10Bit AD/DACs w/FIFO Temp Sns & GPIO Port RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX1040BETX+T 功能描述:ADC / DAC多通道 10Bit AD/DACs w/FIFO Temp Sns & GPIO Port RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
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