參數(shù)資料
型號(hào)： MAX104
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： ADC
英文描述： 【5V, 1Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier
中文描述： 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PGA192
文件頁(yè)數(shù)： 15/32頁(yè)
文件大小： 637K
代理商： MAX104
Non-Demultiplexed DIV1 Mode
The MAX104 may be operated at up to 500Msps in non-
demultiplexed DIV1 mode (Table 2). In this mode, the
internal demultiplexer is disabled, and sampled data is
presented to the primary port only, with the data repeat-
ed at the auxiliary port but delayed by one clock cycle
(Figure 6). Since the auxiliary output port contains the
same data stream as the primary output port, the auxil-
iary port can be shut down to save power by connecting
AUXEN1 and AUXEN2 to digital ground (GNDD). This
powers down the internal bias cells and causes both
outputs (true and complementary) of the auxiliary port to
pull up to a logic-high level. To save additional power,
the external 50
termination resistors connected to the
PECL termination power supply (V
CC
O - 2V) may be
removed from all auxiliary output ports.
Demultiplexed DIV2 Mode
The MAX104 features an internally selectable DIV2
mode (Table 2) that reduces the output data rate to
one-half of the sample clock rate. The demultiplexed
outputs are presented in dual 8-bit format with two con-
secutive samples appearing in the primary and auxil-
iary output ports on the rising edge of the data-ready
clock (Figure 7). The auxiliary data port contains the
previous sample, and the primary output contains the
most recent data sample. AUXEN1 and AUXEN2 must
be connected to V
CC
O to power-up the auxiliary port
PECL output drivers.
M
±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Trac k/Hold Amplifier
______________________________________________________________________________________
15
NOTE:
THE AUXILIARY PORT DATA IS DELAYED ONE ADDITIONAL CLOCK CYCLE FROM THE PRIMARY PORT DATA.
GROUNDING AUXEN1 AND AUXEN2 WILL POWER DOWN THE AUXILIARY PORT TOSAVE POWER.
CLK-
CLK+
n
n+1
n+2
n+3
n+4
n+5
n+1
n+2
n+3
n+4
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
ADC SAMPLE NUMBER
ADC SAMPLES ON THE RISING EDGE OF CLK+
CLK
DREADY
AUXILIARY
DATA PORT
PRIMARY
DATA PORT
DREADY+
DREADY-
Figure 6. Non-Demuxed, DIV1-Mode Timing Diagram
NOTE:
THE LATENCY TOTHE PRIMARY PORT IS 7.5 CLOCK CYCLES, AND THE LATENCY TOTHE AUXILIARY PORT IS 8.5 CLOCK CYCLES.
BOTH THE PRIMARY AND AUXILIARY DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK.
CLK-
CLK+
n
n+1
n+2
n+3
n+4
n+5
n+1
n-1
n+3
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
ADC SAMPLE NUMBER
ADC SAMPLES ON THE RISING EDGE OF CLK+
CLK
DREADY
AUXILIARY
DATA PORT
PRIMARY
DATA PORT
DREADY+
DREADY-
n
n+2
n+4
Figure 7. Demuxed DIV2-Mode Timing Diagram
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