參數(shù)資料
型號(hào)： MAX101CFR
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： ADC
英文描述： 500Msps, 8-Bit ADC with Track/Hold
中文描述： DUAL 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP84
封裝： HEAT SINK, CERAMIC, FP-84
文件頁(yè)數(shù)： 7/16頁(yè)
文件大小： 116K
代理商： MAX101CFR
M
500Msps, 8-Bit ADC with Trac k/Hold
_______________________________________________________________________________________
7
______________________________________________________________Pin Desc ription
32, 69, 80
V
EE
31
DCLK
Complementary Differential Clock Outputs. Used to synchronize following circuitry: Outputs A0–A7
are valid after DCLK’s rising edge. B0–B7 output data are valid after DCLK’s falling edge (see Figure 1
for output timing information).
Negative Power Supply, -5.2V ±5% nominal
16, 48, 63
N.C.
35
10
VB
RBS
“B” side negative reference voltage sense (Note 9)
DIV10
Divide by 10 mode. Leave open for normal operation. Selects test mode when grounded.
36, 38, 39,
41, 42, 44,
45, 47
A7–A0
29
SUB
No Connect—no internal connection to these pins.
12
TP3
5, 59
TRK1
Phasing inputs (normally left open). See Applications Informationsection.
8, 21, 43,
56, 81
V
CC
Positive Power Supply, +5V ±5% nominal
11
TP4
Internal connection, leave pin open.
13
VB
RTS
“B” side positive reference voltage sense (Note 9)
9
VB
RB
“B” side negative reference voltage input (Note 9)
3, 61
CLK
Complementary Differential Clock Inputs. Can be driven from standard 10KH ECL with the following
considerations: Internally, pins 2, 62 and 3, 61 are the ends of a 50
transmission line. Either end
can be driven with the other end terminated with 50
to -2V. See Typical Operating Circuit
4, 7, 15, 18,
24, 27, 30,
34, 37, 40,
46, 49, 57,
60, 64, 67,
68, 70, 71,
74, 77, 78,
79, 82, 84
GND
Power-Supply Ground
2, 62
CLK
NAME
FUNCTION
1
PAD
Internal connection, leave open.
PIN
14
VB
RT
“B” side positive reference voltage input (Note 9)
Internal connection, leave pin open.
Circuit Substrate contact. This pin
must
be connected to V
EE
.
33
DCLK
28, 26, 25,
23, 22, 20,
19, 17
B7–B0
AData and BData Outputs. A0 and B0 are the LSBs, and A7 and B7 are the MSBs. AData and BData
outputs conform to ECL logic swings and drive 100
transmission lines. Terminate with 100
to -2V
(120
for Tj > +100°C). See Figures 1–3.
6, 58
TRK1
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