參數(shù)資料
型號(hào): MAX101CFR
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): ADC
英文描述: 500Msps, 8-Bit ADC with Track/Hold
中文描述: DUAL 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP84
封裝: HEAT SINK, CERAMIC, FP-84
文件頁(yè)數(shù): 12/16頁(yè)
文件大?。?/td> 116K
代理商: MAX101CFR
M
500Msps, 8-Bit ADC with Trac k/Hold
12
______________________________________________________________________________________
For single-ended operation:
1) Apply a DC offset to one of the analog inputs, or
leave one input open. (Both AIN+ and AIN- are ter-
minated internally with 50
to analog ground.)
2) Drive the other input with a ±250mV + offset to
obtain either full- or zero-scale digital output. If a DC
common-mode offset is used, the total voltage swing
allowed is ±500mV (analog signal plus offset with
respect to ground).
Referenc e
The ADC’s reference resistor is a Kelvin-sensed, resis-
tor string that sets the ADC’s LSB size and dynamic
operating range. Normally, the top and bottom of this
string are driven with an external buffer amplifier. It will
need to supply approximately 19mA due to the 100
minimum resistor string impedance. A ±0.95V refer-
ence voltage is normally applied to inputs VA
RT
, VB
RT
,
VA
RB
, and VB
RB
. The reference inputs VA
RTS
, VA
RBS
,
VB
RTS
, and VB
RBS
allow Kelvin sensing of the applied
voltages to increase precision.
An RC network at the ADC’s reference terminals is
needed for best performance. This network consists of
a 33
resistor connected in series with the buffer out-
put that drives the reference. A 0.47μF capacitor must
be connected near the resistor at the buffer’s output
(see Typical Operating Circuit). This resistor and
capacitor combination should be located within 0.5
inches of the MAX101A package. Any noise on these
pins will directly affect the code uncertainty and
degrade the ADC’s effective-bits performance.
R
R
R
PARASITIC
RESISTANCE
TO
COMPARATORS
POSITIVE
REFERENCE
NEGATIVE
REFERENCE
R
R
VA
RBS
VA
RB
VA
RT
VA
RTS
PARASITIC
RESISTANCE
Figure 5. Reference Ladder
Table 2. Input Voltage Range
* An offset V
IO
, as specified in the DC electrical parameters, will
be present at the input. Compensate for this offset by adjusting
the reference voltage. Offsets may be different between side A
and side B.
INPUT
AIN+
(mV)
+125
AIN-
(mV)
-125
OUTPUT
CODE
1 1 1 1 1 1 1 1
MSB to
LSB
full scale
Differential
0
0
1 0 0 0 0 0 0 0
mid scale
-125
+125
0 0 0 0 0 0 0 0 zero scale
+250
0
1 1 1 1 1 1 1 1
full scale
0
0
1 0 0 0 0 0 0 0
mid scale
-250
0
0 0 0 0 0 0 0 0 zero scale
Single
Ended
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