參數(shù)資料
型號: MAX101CFR
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 500Msps, 8-Bit ADC with Track/Hold
中文描述: DUAL 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP84
封裝: HEAT SINK, CERAMIC, FP-84
文件頁數(shù): 4/16頁
文件大?。?/td> 116K
代理商: MAX101CFR
M
500Msps, 8-Bit ADC with Trac k/Hold
4
_______________________________________________________________________________________
DIV10 = 0, Figures 1 and 2
DIV10 = 0, Figures 1 and 2
ns
CLK, CLK
CLK, CLK
0.7
1.3
1.8
t
PD2
DCLK to A/BData
Propagation Delay
DCLK
DATA
DCLK
DATA
20% to 80%
ps
800
t
F
ns
1.2
2.3
3.4
t
PD1
CLK to DCLK
Propagation Delay
CONDITIONS
20% to 80%
300
Clock
Cycles
t
NPD
Figures 2, 3
Pipeline Delay (Latency)
15
15
ps
500
t
R
Fall Time
300
Rise Time
ns
0.9
2.5
t
PWH
ns
0.9
2.5
t
PWL
Clock Pulse Width Low
Clock Pulse Width High
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
TIMING CHARACTERISTICS
(V
EE
= -5.2V, V
CC
= +5V, R
L
= 100
to -2V, VA
RT
, VB
RT
= 0.95V, VA
RB
, VB
RB
= -0.95V, T
A
= +25°C, unless otherwise noted.)
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
All devices are 100% production tested at +25°C and are guaranteed by design for T
A
= T
MIN
to T
MAX
as specified.
Deviation from best-fit straight line. See Integral Nonlinearity section.
See the Signal-to-Noise Ratio and Effective Bits section in the Detailed Description of Specifications.
SNR calculated from effective bits performance using the following equation: SNR(dB) = 1.76 + 6.02 x effective bits.
Clock pulse width minimum requirements t
PWL
and t
PWH
must be observed to achieve stated performance.
Outputs terminated through 100
to -2.0V.
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
-0.75
0.75
0
256
-0.50
0.50
M
OUTPUT CODE
I
64
192
128
0
-0.25
0.25
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
-0.75
0.75
0
256
-0.50
0.50
M
OUTPUT CODE
D
64
192
128
0
-0.25
0.25
__________________________________________Typic al Operating Charac teristic s
(V
EE
= -5.2V, V
CC
= +5V, R
L
= 100
to -2V, VA
RT
, VB
RT
= 0.95V, VA
RB
, VB
RB
= -0.95V, T
A
= +25°C, unless otherwise noted.)
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