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參數(shù)資料
| 型號： | M3822 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 8 Bits Microcomputer(8位單片機) |
| 中文描述： | 單芯片8位單片機（8位單片機） |
| 文件頁數(shù)： | 49/52頁 |
| 文件大?。?/td> | 781K |
| 代理商： | M3822 |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3822 Group
49
Measurement output pin
100 pF
CMOS output
Note :
When bit 4 of the UART
control register (address 001B
16
) is “1”.
(N-channel open-drain output mode)
N-channel open-drain output (Note)
1 k
100 pF
Measurement output pin
SWITCHING CHARACTERISTICS 1
(V
CC
= 4.0 to 5.5 V, V
SS =
0 V, T
a
= –20 to 85
°
C, unless otherwise noted.
Extended operating temperature version : V
CC
= 3.0 to 5.5 V, T
a
= –40 to –20
°
C and V
CC
= 2.5 to 5.5 V, T
a
= –20 to 85
°
C)
Notes 1 :
When the P4
5
/T
X
D P-channel output disable bit of the UART control register (bit 4 of address 001B
16
) is “0”.
2 :
X
OUT
and X
COUT
pins are excluded.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
140
30
30
30
30
Symbol
Parameter
Limits
Typ.
Min.
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
c(S
CLK
)
/2–30
t
c(S
CLK
)
/2–30
–30
10
10
Max.
t
wH(S
CLK
)
t
wL(S
CLK
)
t
d(S
CLK
–T
X
D)
t
v(S
CLK
–T
X
D)
t
r(S
CLK
)
t
f(S
CLK
)
t
r(CMOS)
t
f(CMOS)
Fig. 37 Circuit for measuring output switching characteristics (1)
SWITCHING CHARACTERISTICS 2
(V
CC
= 2.5 to 4.0 V, V
SS =
0 V, T
a
= –20 to 85
°
C, unless otherwise noted.
Extended operating temperature version : V
CC
= 3.0 to 5.5 V, T
a
= –40 to –20
°
C and V
CC
= 2.5 to 5.5 V, T
a
= –20 to 85
°
C)
Notes 1 :
When the P4
5
/T
X
D P-channel output disable bit of the UART control register (bit 4 of address 001B
16
) is “0”.
2 :
X
OUT
and X
COUT
pins are excluded.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
350
50
50
50
50
Symbol
Parameter
Limits
Typ.
Min.
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
c(S
CLK
)
/2–50
t
c(S
CLK
)
/2–50
–30
20
20
Max.
t
wH(S
CLK
)
t
wL(S
CLK
)
t
d(S
CLK
–T
X
D)
t
v(S
CLK
–T
X
D)
t
r(S
CLK
)
t
f(S
CLK
)
t
r(CMOS)
t
f(CMOS)
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