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參數(shù)資料
| 型號： | M3822 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 8 Bits Microcomputer(8位單片機) |
| 中文描述： | 單芯片8位單片機（8位單片機） |
| 文件頁數(shù)： | 29/52頁 |
| 文件大?。?/td> | 781K |
| 代理商： | M3822 |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3822 Group
LCD DRIVE CONTROL CIRCUIT
The 3822 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
LCD display RAM
Segment output enable register
LCD mode register
Selector
Timing controller
Common driver
Segment driver
Bias control circuit
A maximum of 32 segment output pins and 4 common output pins
can be used.
Up to 128 pixels can be controlled for LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register,
Fig. 22 Structure of segment output enable register and LCD mode register
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automati-
cally, performs the bias control and the duty ratio control, and dis-
plays the data on the LCD panel.
Table 2. Maximum number of display pixels at each
duty ratio
Duty ratio
Maximum number of display pixel
64 dots
or 8 segment LCD 8 digits
96 dots
or 8 segment LCD 12 digits
128 dots
or 8 segment LCD 16 digits
2
3
4
Segment output enable bit 0
0 : Input ports P3
4
–P3
7
1 : Segment output SEG
12
–SEG
15
Segment output enable bit 1
0 : I/O ports P0
0
, P0
1
1 : Segment output SEG
16
,SEG
17
Segment output enable bit 2
0 : I/O ports P0
2
–P0
7
1 : Segment output SEG
18
–SEG
23
Segment output enable bit 3
0 : I/O ports P1
0
,P1
1
1 : Segment output SEG
24
,SEG
25
Segment output enable bit 4
0 : I/O port P1
2
1 : Segment output SEG
26
Segment output enable bit 5
0 : I/O ports P1
3
–P1
7
1 : Segment output SEG
27
–SEG
31
Not used (return “0” when read)
(Do not write “1” to this bit)
Segment output enable register
(SEG : address 0038
16
)
b7
b0
LCD mode register
(LM : address 0039
16
)
Duty ratio selection bits
0 0 : Not available
0 1 : 2 (use COM
0
,COM
1
)
1 0 : 3 (use COM
0
–COM
2
)
1 1 : 4 (use COM
0
–COM
3
)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used (returns “0” when read)
(Do not write “1” to this bit)
LCD circuit divider division ratio selection bits
0 0 : CLOCK input
0 1 : 2 division of CLOCK input
1 0 : 4 division of CLOCK input
1 1 : 8 division of CLOCK input
LCDCK count source selection bit (Note)
0 : f(X
CIN
)/32
1 : f(X
IN
)/8192
Note :
LCDCK is a clock for a LCD timing controller.
b7
b0
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