參數(shù)資料
型號(hào)： M3822
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 8 Bits Microcomputer(8位單片機(jī))
中文描述： 單芯片8位單片機(jī)（8位單片機(jī)）
文件頁(yè)數(shù)： 17/52頁(yè)
文件大?。?/td> 781K
代理商： M3822
17
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3822 Group
INTERRUPTS
Interrupts occur by seventeen sources: eight external, eight inter-
nal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are “1” and the inter-
rupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
Interrupt Operation
When an interrupt is received, the contents of the program counter
and processor status register are automatically stored into the
stack. The interrupt disable flag is set to inhibit other interrupts
from interfering.The corresponding interrupt request bit is cleared
and the interrupt jump destination address is read from the vector
table into the program counter.
Notes on Use
When the active edge of an external interrupt (INT
0
–INT
3
, CNTR
0
,
or CNTR
1
) is changed, the corresponding interrupt request bit
may also be set. Therefore, please take following sequence;
(1) Disable the external interrupt which is selected.
(2) Change the active edge selection.
(3) Clear the interrupt request bit which is selected to “0”.
(4) Enable the external interrupt which is selected.
Notes 1
: Vector addresses contain interrupt jump destination addresses.
2
: Reset function in the same way as an interrupt with the highest priority.
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT
0
input
At detection of either rising or
falling edge of INT
1
input
At completion of serial I/O data
reception
At completion of serial I/O
transmit shift or when transmission
buffer is empty
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR
0
input
At detection of either rising or
falling edge of CNTR
1
input
At timer 1 underflow
At detection of either rising or
falling edge of INT
2
input
At detection of either rising or
falling edge of INT
3
input
At falling of conjunction of input
level for port P2 (at input mode)
At falling of ADT input
At completion of A-D conversion
At BRK instruction execution
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(valid when an “L” level is applied)
Valid when ADT interrupt is
selected External interrupt
(valid at falling)
Valid when A-D interrupt is
selected
Non-maskable software interrupt
Interrupt Source
Reset (Note 2)
INT
0
INT
1
Serial I/O
reception
Serial I/O
transmission
Timer X
Timer Y
Timer 2
Timer 3
CNTR
0
CNTR
1
Timer 1
INT
2
INT
3
Key input
(Key-on wake up)
ADT
A-D conversion
BRK instruction
Low
FFFC
16
FFFA
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
FFE0
16
FFDE
16
FFDC
16
High
FFFD
16
FFFB
16
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFE1
16
FFDF
16
FFDD
16
Table 1. Interrupt vector addresses and priority
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Vector Addresses (Note 1)
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