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| 型號(hào)： | M38049FFSP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 79/135頁(yè) |
| 文件大?。?/td> | 2055K |
| 代理商： | M38049FFSP |
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79
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
[I
2
C Special Mode Status Register (S3)]
0012
16
The I
2
C special mode status register (S3: address 0012
16
) con-
sists of the flags indicating I
2
C operating state in the I
2
C special
mode, which is set by the I
2
C special mode control register (S3D:
address 0017
16
).
The stop condition flag is valid in all operating modes.
Bit 0: Slave address 0 comparison flag (AAS0)
Bit 1: Slave address 1 comparison flag (AAS1)
Bit 2: Slave address 2 comparison flag (AAS2)
These flags indicate a comparison result of address data. These
flags are valid only when the slave address control bit (MSLAD) is
“
1
”
.
In the 7-bit addressing format of the slave reception mode, the re-
spective slave address i (i = 0, 1, 2) comparison flags
corresponding to the I
2
C slave address registers 0 to 2 are set to
“
1
”
when an address data immediately after an occurrence of a
START condition agrees with the high-order 7-bit slave address
stored in the I
2
C slave address registers 0 to 2 (addresses 0FF7
16
to 0FF9
16
).
In the 10-bit addressing format of the slave mode, the respective
slave address i (i = 0, 1, 2) comparison flags corresponding to the
I
2
C slave address registers are set to
“
1
”
when an address data is
compared with the 8 bits consisting of the slave address stored in
the I
2
C slave address registers 0 to 2 and the RWB bit, and the
first byte agrees.
These flags are initialized to
“
0
”
at reset, when the slave address
control bit (MSLAD) is
“
0
”
, or when writing data to the I
2
C data
shift register (S0: address 0011
16
).
Bit 5: SCL pin low hold 2 flag (PIN2)
When the ACK interrupt control bit (ACKICON) and the ACK clock
bit (ACK) are
“
1
”
, this flag is set to
“
0
”
in synchronization with the
falling of the data
’
s last SCL clock, just before the ACK clock. The
SCL pin is simultaneously held low, and the I
2
C interrupt request
occurs.
This flag is initialized to
“
1
”
at reset, when the ACK interrupt con-
trol bit (ACKICON) is
“
0
”
, or when writing
“
1
”
to the SCL pin low
hold 2 flag set bit (PIN2IN).
The SCL pin is held low when either the SCL pin low hold bit (PIN)
or the SCL pin low hold 2 flag (PIN2) becomes
“
0
”
. The low hold
state of the SCL pin is released when both the SCL pin low hold
bit (PIN) and the SCL pin low hold 2 flag (PIN2) are
“
1
”
.
Bit 7: Stop condition flag (SPCF)
This flag is set to
“
1
”
when a STOP condition occurs.
This flag is initialized to
“
0
”
at reset, when the I
2
C-BUS interface
enable bit (ES0) is
“
0
”
, or when writing
“
1
”
to the STOP condition
flag clear bit (SPFCL).
Fig. 75 Structure of I
2
C special mode status register
b
7
b
A
0
I
2
C
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0
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2
P
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N
2
SPCF
Slave address 1 comparison flag
0 : Address disagreement
1 : Address agreement
Sl
a
0
1
v
e
: A
: A
a
d
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w
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:
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