參數(shù)資料
型號： M38049FFSP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 55/135頁
文件大小： 2055K
代理商： M38049FFSP
55
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3. S
RDY
output of reception side
G
Note
When signals are output from the S
RDY
pin on the reception side
by using an external clock in the clock synchronous serial I/O
mode, set all of the receive enable bit, the S
RDY
output enable bit,
and the transmit enable bit to
“
1
”
(transmit enabled).
4. Setting serial I/O control register again
G
Note
Set the serial I/O control register again after the transmission and
the reception circuits are reset by clearing both the transmit en-
able bit and the receive enable bit to
“
0.
”
5. Data transmission control with referring to transmit shift
register completion flag
G
Note
The transmit shift register completion flag changes from
“
1
”
to
“
0
”
with a delay of 0.5 to 1.5 shift clocks. When data transmission is
controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
6. Transmission control when external clock is selected
G
Note
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to
“
1
”
at
“
H
”
of the S
CLK
input level. Also, write data to the transmit buffer register at
“
H
”
of
the S
CLK
input level.
7. Transmit interrupt request when transmit enable bit is set
G
Note
When using the transmit interrupt, take the following sequence.
Set the serial I/O transmit interrupt enable bit to
“
0
”
(disabled).
Set the transmit enable bit to
“
1
”
.
Set the serial I/O transmit interrupt request bit to
“
0
”
after 1 or
more instruction has executed.
Set the serial I/O transmit interrupt enable bit to
“
1
”
(enabled).
G
Reason
When the transmit enable bit is set to
“
1
”
, the transmit buffer
empty flag and the transmit shift register shift completion flag are
also set to
“
1
”
. Therefore, regardless of selecting which timing for
the generating of transmit interrupts, the interrupt request is gener-
ated and the transmit interrupt request bit is set at this point.
Clear both the transmit enable bit
(TE) and the receive enable bit
(RE) to
“
0
”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O control register
↓
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to
“
1
”
Can be set with the
LDM
instruction at the
same time
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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