
125
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Table 37 Switching characteristics 1
(V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, T
a
=
–
20 to 85
°
C, unless otherwise noted)
Table 38 Switching characteristics 2
(V
CC
= 2.7 to 4.0 V, V
SS
= 0 V, T
a
=
–
20 to 85
°
C, unless otherwise noted)
Serial I/O1, serial I/O3 clock output
“
H
”
pulse width
Serial I/O1, serial I/O3 clock output
“
L
”
pulse width
Serial I/O1, serial I/O3 output delay time
(Note 1)
Serial I/O1, serial I/O3 output valid time
(Note 1)
Serial I/O1, serial I/O3 clock output rising time
Serial I/O1, serial I/O3 clock output falling time
Serial I/O2 clock output
“
H
”
pulse width
Serial I/O2 clock output
“
L
”
pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time
(Note 2)
CMOS output falling time
(Note 2)
t
WH
(S
CLK1
),
t
WH
(S
CLK3
)
t
WL
(S
CLK1
),
t
WL
(S
CLK3
)
t
d
(S
CLK1
-T
X
D1) ,
t
d
(S
CLK3
-T
X
D3)
t
v
(S
CLK1
-T
X
D1) ,
t
v
(S
CLK3
-T
X
D3)
t
r
(S
CLK1
) , t
r
(S
CLK3
)
t
f
(S
CLK1
), t
f
(S
CLK3
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
d
(S
CLK2
-S
OUT2
)
t
V
(S
CLK2
-S
OUT2
)
t
f
(S
CLK2
)
t
r
(CMOS)
t
f
(CMOS)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
t
C
(S
CLK1
)/2
–
30
t
C
(S
CLK3
)/2
–
30
t
C
(S
CLK1
)/2
–
30
t
C
(S
CLK3
)/2
–
30
–
30
t
C
(S
CLK2
)/2
–
160
t
C
(S
CLK2
)/2
–
160
0
Typ.
10
10
Max.
140
30
30
200
30
30
30
Symbol
Unit
Notes 1:
When the P4
5
/T
X
D1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B
16
) is
“
0
”
.
When the P3
5
/T
X
D3 P-channel output disable bit of the UART3 control register (bit 4 of address 0033
16
) is
“
0
”
.
2:
The X
OUT
pin is excluded.
Test
conditions
Fig. 105
Serial I/O1, serial I/O3 clock output
“
H
”
pulse width
Serial I/O1, serial I/O3 clock output
“
L
”
pulse width
Serial I/O1, serial I/O3 output delay time
(Note 1)
Serial I/O1, serial I/O3 output valid time
(Note 1)
Serial I/O1, serial I/O3 clock output rising time
Serial I/O1, serial I/O3 clock output falling time
Serial I/O2 clock output
“
H
”
pulse width
Serial I/O2 clock output
“
L
”
pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time
(Note 2)
CMOS output falling time
(Note 2)
t
WH
(S
CLK1
),
t
WH
(S
CLK3
)
t
WL
(S
CLK1
),
t
WL
(S
CLK3
)
t
d
(S
CLK1
-T
X
D1) ,
t
d
(S
CLK3
-T
X
D3)
t
v
(S
CLK1
-T
X
D1) ,
t
v
(S
CLK3
-T
X
D3)
t
r
(S
CLK1
) , t
r
(S
CLK3
)
t
f
(S
CLK1
), t
f
(S
CLK3
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
d
(S
CLK2
-S
OUT2
)
t
V
(S
CLK2
-S
OUT2
)
t
f
(S
CLK2
)
t
r
(CMOS)
t
f
(CMOS)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
t
C
(S
CLK1
)/2
–
50
t
C
(S
CLK3
)/2
–
50
t
C
(S
CLK1
)/2
–
50
t
C
(S
CLK3
)/2
–
50
–
30
t
C
(S
CLK2
)/2
–
240
t
C
(S
CLK2
)/2
–
240
0
Typ.
20
20
Max.
350
50
50
400
50
50
50
Symbol
Unit
Notes 1:
When the P4
5
/T
X
D1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B
16
) is
“
0
”
.
When the P3
5
/T
X
D3 P-channel output disable bit of the UART3 control register (bit 4 of address 0033
16
) is
“
0
”
.
2:
The X
OUT
pin is excluded.
Test
conditions
Fig. 105